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AD9173 Datasheet(PDF) 114 Page - Analog Devices

Part # AD9173
Description  Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9173 Datasheet(HTML) 114 Page - Analog Devices

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Data Sheet
AD9173
REGISTER DETAILS
analog.com
Rev. C | 114 of 144
Table 60. Register Details
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
5
PHADJ_RD
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
[4:0]
LL_LID0
Received ILAS LID configuration on Lane 0. This
control is paged by the LINK_PAGE control in
Register 0x300.
0x0
R
0x403
SCR_L_REG
7
SCR_RD
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
0
Scrambling is disabled.
1
Scrambling is enabled.
[6:5]
RESERVED
Reserved.
0x0
R
[4:0]
L_RD-1
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
00000
1 lane per converter device.
00001
2 lanes per converter device.
00010
3 lanes per converter device.
00011
4 lanes per converter device.
0x404
F_REG
[7:0]
F_RD-1
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
0
1 octet per frame.
1
2 octets per frame.
10
3 octets per frame.
11
4 octets per frame.
0x405
K_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
K_RD-1
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
00000
Default value.
11111
32 frames per multiframe.
0x406
M_REG
[7:0]
M_RD-1
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
0x407
CS_N_REG
[7:6]
CS_RD
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
5
RESERVED
Reserved.
0x0
R
[4:0]
N_RD-1
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
0x408
NP_REG
[7:5]
SUBCLASSV_RD
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
[4:0]
NP_RD-1
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
0x409
S_REG
[7:5]
JESDV_RD-1
Received ILAS configuration on Lane 0. This control
is paged by the LINK_PAGE control in Register
0x300.
0x0
R
000
JESD204A.



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