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AD9173 Datasheet(PDF) 116 Page - Analog Devices

Part # AD9173
Description  Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9173 Datasheet(HTML) 116 Page - Analog Devices

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Data Sheet
AD9173
REGISTER DETAILS
analog.com
Rev. C | 116 of 144
Table 60. Register Details
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
[4:0]
LL_LID4
Received ILAS LID configuration on Lane 4. This
control is paged by the LINK_PAGE control in
Register 0x300.
0x0
R
0x42D
CHECKSUM4_REG
[7:0]
LL_FCHK4
Received checksum during ILAS on Lane 4. This
control is paged by the LINK_PAGE control in
Register 0x300.
0x0
R
0x42E
COMPSUM4_REG
[7:0]
LL_FCMP4
Computed checksum on Lane 4. This control is paged
by the LINK_PAGE control in Register 0x300.
0x0
R
0x432
LID5_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LL_LID5
Received ILAS LID configuration on Lane 5. This
control is paged by the LINK_PAGE control in
Register 0x300.
0x0
R
0x435
CHECKSUM5_REG
[7:0]
LL_FCHK5
Received checksum during ILAS on Lane 5. This
control is paged by the LINK_PAGE control in
Register 0x300.
0x0
R
0x436
COMPSUM5_REG
[7:0]
LL_FCMP5
Computed checksum on Lane 5. This control is paged
by the LINK_PAGE control in Register 0x300.
0x0
R
0x43A
LID6_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LL_LID6
Received ILAS LID configuration on Lane 6. This
control is paged by the LINK_PAGE control in
Register 0x300.
0x0
R
0x43D
CHECKSUM6_REG
[7:0]
LL_FCHK6
Received checksum during ILAS on Lane 6. This
control is paged by the LINK_PAGE control in
Register 0x300.
0x0
R
0x43E
COMPSUM6_REG
[7:0]
LL_FCMP6
Computed checksum on Lane 6. This control is paged
by the LINK_PAGE control in Register 0x300.
0x0
R
0x442
LID7_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LL_LID7
Received ILAS LID configuration on Lane 7. This
control is paged by the LINK_PAGE control in
Register 0x300.
0x0
R
0x445
CHECKSUM7_REG
[7:0]
LL_FCHK7
Received checksum during ILAS on Lane 7. This
control is paged by the LINK_PAGE control in
Register 0x300.
0x0
R
0x446
COMPSUM7_REG
[7:0]
LL_FCMP7
Computed checksum on Lane 7. This control is paged
by the LINK_PAGE control in Register 0x300.
0x0
R
0x450
ILS_DID
[7:0]
DID
Device (link) identification number. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R/W
0x451
ILS_BID
[7:0]
BID
Bank ID, extension to DID. This control is paged by
the LINK_PAGE control in Register 0x300. This signal
must only be programmed while the QBD is held in
soft reset (Register 0x475, Bit 3), and must not be
changed during normal operation.
0x0
R/W
0x452
ILS_LID0
7
RESERVED
Reserved.
0x0
R
6
ADJDIR
Direction to adjust the DAC LMFC. Link information is
received on Link Lane 0 as specified in Section 8.3 of
JESD204B. Only Link 0 is supported. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R/W
5
PHADJ
Phase adjustment request to the DAC. Only Link 0 is
supported. This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R/W
[4:0]
LID0
Lane identification number (within link). This control is
paged by the LINK_PAGE control in Register 0x300.
This signal must only be programmed while the QBD
0x0
R/W



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