AD9173 datasheet(113/144 Pages) AD

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Data Sheet

AD9173

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Rev. C | 113 of 144

Table 60. Register Details

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

1111

Sample 15.

[3:2]

SHORT_TPL_M_SEL

Short transport layer test channel select. Select which

channel of the DAC to check.

0x0

R/W

Channel 0.

Channel 1.

Channel 2.

SHORT_TPL_TEST_

RESET

Short transport layer test reset. Resets the result of

short transport layer test.

0x0

R/W

Not reset.

Reset.

SHORT_TPL_TEST_

Short transport layer test enable. Enable short

transport layer test.

0x0

R/W

Disable.

Enable.

0x32D

SHORT_TPL_TEST_1

[7:0]

SHORT_TPL_REF_

SP_LSB

Short transport layer reference sample, LSB. This

bit field is the lower eight bits of the expected DAC

sample during the short transport layer test and is

used to compare with the received sample at the

JESD204B Rx output.

0x0

R/W

0x32E

SHORT_TPL_TEST_2

[7:0]

SHORT_TPL_REF_

SP_MSB

Short transport layer test reference sample, MSB.

This bit field is the upper eight bits of the expected

DAC sample during the short transport layer test and

is used to compare with the received sample at the

JESD204B Rx output.

0x0

R/W

0x32F

SHORT_TPL_TEST_3

RESERVED

Reserved.

0x0

R/W

SHORT_TPL_IQ_

SAMPLE_SEL

Selects I or Q of the DAC to check the testing of the

short transport layer.

Select I data to test.

Select Q data to test.

[5:1]

RESERVED

Reserved.

0x0

R/W

SHORT_TPL_FAIL

Short transport layer test fail. This bit shows if the

selected DAC sample matches the expected sample

for the short transport layer test. If they match, the

test passes; otherwise, the test fails.

0x0

Test pass.

Test fail.

0x334

JESD_BIT_INVERSE_

CTRL

[7:0]

JESD_BIT_INVERSE

Logical lane invert. Each bit of this control inverses

the JESD204B deserialized data from one specific

JESD204B Rx PHY. Set Bit x high to invert the

JESD204B deserialized data on Logical Lane x.

0x0

R/W

0x400

DID_REG

[7:0]

DID_RD

Received ILAS configuration on Lane 0. This control

is paged by the LINK_PAGE control in Register

0x300.

0x0

0x401

BID_REG

[7:0]

BID_RD

Received ILAS configuration on Lane 0. This control

is paged by the LINK_PAGE control in Register

0x300.

0x0

0x402

LID0_REG

RESERVED

Reserved.

0x0

ADJDIR_RD

Received ILAS configuration on Lane 0. This control

is paged by the LINK_PAGE control in Register

0x300.

0x0

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