AD9173 datasheet(129/144 Pages) AD

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Data Sheet

AD9173

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Rev. C | 129 of 144

Table 60. Register Details

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while the QBD

is held in soft reset (Register 0x475, Bit 3), and must

not be changed during normal operation.

0x48D

ECNT_TCH5

[7:3]

RESERVED

Reserved.

0x0

[2:0]

ECNT_TCH5

Terminal count hold enable of error counters for

Lane 5. This control is paged by the LINK_PAGE

control in Register 0x300. When set, the designated

counter is to hold the terminal count value of 0xFF

when it is reached until the counter is reset by the

user. Otherwise, the designated counter rolls over.

Counters of each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while the QBD

is held in soft reset (Register 0x475, Bit 3), and must

not be changed during normal operation.

0x48E

ECNT_TCH6

[7:3]

RESERVED

Reserved.

0x0

[2:0]

ECNT_TCH6

Terminal count hold enable of error counters for

Lane 6. This control is paged by the LINK_PAGE

control in Register 0x300. When set, the designated

counter is to hold the terminal count value of 0xFF

when it is reached until the counter is reset by the

user. Otherwise, the designated counter rolls over.

Counters of each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while the QBD

is held in soft reset (Register 0x475, Bit 3), and must

not be changed during normal operation.

0x48F

ECNT_TCH7

[7:3]

RESERVED

Reserved.

0x0

[2:0]

ECNT_TCH7

Terminal count hold enable of error counters for

Lane 7. This control is paged by the LINK_PAGE

control in Register 0x300. When set, the designated

counter is to hold the terminal count value of 0xFF

when it is reached until the counter is reset by the

user. Otherwise, the designated counter rolls over.

Counters of each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

This signal must only be programmed while the QBD

is held in soft reset (Register 0x475, Bit 3), and must

not be changed during normal operation.

0x490

ECNT_STAT0

[7:4]

RESERVED

Reserved.

0x0

LANE_ENA0

This output indicates if Lane 0 is enabled. This control

is paged by the LINK_PAGE control in Register

0x300.

0x0

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