AD9173 datasheet(127/144 Pages) AD

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Data Sheet

AD9173

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Rev. C | 127 of 144

Table 60. Register Details

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

[5:3]

ECNT_ENA5

Error counter enables for Lane 5. This control is

paged by the LINK_PAGE control in Register 0x300.

Counters of each lane are addressed as follows:

0x7

R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0]

ECNT_RST5

Reset error counters for Lane 5. This control is

paged by the LINK_PAGE control in Register 0x300.

Counters of each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x486

ECNT_CTRL6

[7:6]

RESERVED

Reserved.

0x0

[5:3]

ECNT_ENA6

Error counter enables for Lane 6. This control is

paged by the LINK_PAGE control in Register 0x300.

Counters of each lane are addressed as follows:

0x7

R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0]

ECNT_RST6

Reset error counters for Lane 6. This control is

paged by the LINK_PAGE control in Register 0x300.

Counters of each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x487

ECNT_CTRL7

[7:6]

RESERVED

Reserved.

0x0

[5:3]

ECNT_ENA7

Error counter enables for Lane 7. This control is

paged by the LINK_PAGE control in Register 0x300.

Counters of each lane are addressed as follows:

0x7

R/W

Bit 5 = unexpected K character error (UEK).

Bit 4 = not in table error (NIT).

Bit 3 = bad disparity error (BDE).

[2:0]

ECNT_RST7

Reset error counters for Lane 7. This control is

paged by the LINK_PAGE control in Register 0x300.

Counters of each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

0x488

ECNT_TCH0

[7:3]

RESERVED

Reserved.

0x0

[2:0]

ECNT_TCH0

Terminal count hold enable of error counters for

Lane 0. This control is paged by the LINK_PAGE

control in Register 0x300. When set, the designated

counter is to hold the terminal count value of 0xFF

when it is reached until the counter is reset by the

user. Otherwise, the designated counter rolls over.

Counters of each lane are addressed as follows:

0x7

R/W

Bit 2 = unexpected K character error (UEK).

Bit 1 = not in table error (NIT).

Bit 0 = bad disparity error (BDE).

AD9173 Datasheet(PDF) 127 Page - Analog Devices

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