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AD9173 Datasheet(PDF) 138 Page - Analog Devices

Part # AD9173
Description  Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9173 Datasheet(HTML) 138 Page - Analog Devices

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Data Sheet
AD9173
REGISTER DETAILS
analog.com
Rev. C | 138 of 144
Table 60. Register Details
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0
CGS7
Code group synchronization status for Lane 7. This
control is paged by the LINK_PAGE control in
Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
0x4B8
JESD_IRQ_ENABLEA
7
EN_BDE
Bad disparity error counter. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
6
EN_NIT
Not in table error counter. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R/W
5
EN_UEK
Unexpected K error counter. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
4
EN_ILD
Interlane deskew. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R/W
3
EN_ILS
Initial lane synchronization. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
2
EN_CKS
Good checksum. This bit compares two checksums:
the checksum that the transmitter sent over the link
during the ILAS and the checksum that the receiver
calculated from the ILAS data that the transmitter sent
over the link. Note that the checksum IRQ only looks
at data sent by the transmitter and not the checksum
programmed into Register 0x45D. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R/W
1
EN_FS
Frame synchronization. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R/W
0
EN_CGS
Code group synchronization. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
0x4B9
JESD_IRQ_ENABLEB
[7:1]
RESERVED
Reserved.
0x0
R
0
EN_ILAS
Configuration mismatch (checked for Lane 0 only).
The ILAS IRQ compares the two sets of ILAS data
obtained by the receiver. The first set of data is
the ILAS data sent over the JESD204B link by the
transmitter. The second set of data is the ILAS data
programmed into the receiver via the SPI (Register
0x450 to Register 0x45D). If any of the data differs,
the IRQ is triggered. Note that all of the ILAS data,
including the checksum, is compared. This control is
paged by the LINK_PAGE control in Register 0x300.
0x0
R/W
0x4BA
JESD_IRQ_STATUSA
7
IRQ_BDE
Bad disparity error counter. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
6
IRQ_NIT
Not in table error counter. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R/W
5
IRQ_UEK
Unexpected K error counter. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
4
IRQ_ILD
Interlane deskew. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R/W
3
IRQ_ILS
Initial lane synchronization. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
2
IRQ_CKS
Good checksum. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R/W
1
IRQ_FS
Frame synchronization. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R/W



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