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AD9173 Datasheet(PDF) 139 Page - Analog Devices |
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AD9173 Datasheet(HTML) 139 Page - Analog Devices |
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139 / 144 page  Data Sheet AD9173 REGISTER DETAILS analog.com Rev. C | 139 of 144 Table 60. Register Details Addr. Name Bits Bit Name Settings Description Reset Access 0 IRQ_CGS Code group synchronization. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R/W 0x4BB JESD_IRQ_STATUSB [7:1] RESERVED Reserved. 0x0 R 0 IRQ_ILAS Configuration mismatch (checked for Lane 0 only). This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R/W 0x4BC IRQ_OUTPUT_MUX_ [7:1] RESERVED Reserved. 0x0 R JESD 0 MUX_JESD_IRQ Selects which IRQ pin is connected to the JESD204B IRQx sources. 0x0 R/W 0 Route the IRQ trigger signal to the IRQ0 pin. 1 Route the IRQ trigger signal to the IRQ1 pin. 0x580 BE_SOFT_OFF_ GAIN_CTRL 7 BE_SOFT_OFF_ GAIN_EN Must be 1 to use soft off/on. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x0 R/W [6:3] RESERVED Reserved. 0x0 R [2:0] BE_GAIN_RAMP_ RATE Sets ramp rate. The gain ramps from 0 to 1 (or 1 to 0) in 32 steps over 2(CODE + 8) DAC clock periods. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x0 R/W 0x581 BE_SOFT_OFF_ ENABLE 7 ENA_SHORT_ PAERR_SOFTOFF Enable short PA error soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x1 R/W 6 ENA_LONG_ PAERR_SOFTOFF Enable long PA error soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x1 R/W [5:4] RESERVED Reserved. 0x0 R 3 ENA_JESD_ERR_ SOFTOFF Enable JESD204B side error soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x0 R/W 2 ROTATE_SOFT_ OFF_EN When set to 1, the synchronization logic rotation triggers the DAC output soft off. Note that Register 0x03B, Bit 0 must also be high. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x1 R/W 1 TXEN_SOFT_OFF_EN When set to 1, a TXENx falling edge triggers the DAC output soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x1 R/W 0 SPI_SOFT_OFF_EN Force a soft off when gain is 1. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x0 R/W 0x582 BE_SOFT_ON_ ENABLE 7 SPI_SOFT_ON_EN Force a soft on when gain is 0. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x0 R/W 6 LONG_LEVEL_ SOFTON_EN When set to 1, this bit enables the long level soft on. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x1 R/W [5:0] RESERVED Reserved. 0x0 R/W 0x583 LONG_PA_ THRES_LSB [7:0] LONG_PA_ THRESHOLD[7:0] Long average power threshold for comparison. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x0 R/W 0x584 LONG_PA_ [7:5] RESERVED Reserved. 0x0 R THRES_MSB [4:0] LONG_PA_ THRESHOLD[12:8] Long average power threshold for comparison. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x0 R/W 0x585 LONG_PA_CONTROL 7 LONG_PA_ENABLE Enable long average power calculation and error detection. This control is paged by the MAINDAC_PAGE control in Register 0x008. 0x0 R/W [6:4] RESERVED Reserved. 0x0 R |
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