AD9173 datasheet(104/144 Pages) AD

104 / 144 page

Data Sheet

AD9173

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Rev. C | 104 of 144

Table 60. Register Details

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

Select Channel 1 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 1, DAC0).

Select Channel 2 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 2, DAC0).

Select Channel 3 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 0, DAC1).

Select Channel 4 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 1, DAC1).

Select Channel 5 for PRBS_COUNT_x and

PRBS_GOOD_x (Channel 2, DAC1).

OR all channels for PRBS_GOOD_x, sum all

channels for PRBS_COUNT_x.

0x151

DECODE_MODE

[7:6]

RESERVED

Reserved.

0x0

R/W

[5:4]

MSB_MODE

MSB shuffling control.

0x0

R/W

[3:0]

RESERVED

Reserved.

0x0

0x1DE

SPI_ENABLE

[7:2]

RESERVED

Reserved.

0x0

SPI_EN1

Enable SPI control.

0x1

R/W

SPI_EN0

Enable SPI control.

0x1

R/W

0x1E2

DDSM_CAL_FTW0

[7:0]

DDSM_CAL_

FTW[7:0]

FTW of the calibration accumulator. This control

is paged by the MAINDAC_PAGE bits in Register

0x008.

0x0

R/W

0x1E3

DDSM_CAL_FTW1

[7:0]

DDSM_CAL_

FTW[15:8]

FTW of the calibration accumulator. This control

is paged by the MAINDAC_PAGE bits in Register

0x008.

0x0

R/W

0x1E4

DDSM_CAL_FTW2

[7:0]

DDSM_CAL_

FTW[23:16]

FTW of the calibration accumulator. This control

is paged by the MAINDAC_PAGE bits in Register

0x008.

0x0

R/W

0x1E5

DDSM_CAL_FTW3

[7:0]

DDSM_CAL_

FTW[31:24]

FTW of the calibration accumulator. This control

is paged by the MAINDAC_PAGE bits in Register

0x008.

0x0

R/W

0x1E6

DDSM_CAL_

[7:3]

RESERVED

Reserved.

0x0

MODE_DEF

DDSM_EN_CAL_

ACC

Enable clock calibration accumulator. This bit must be

first set high, and then must load the calibration FTW

into Register 0x1E2 to Register 0x1E5 to take effect.

This control is paged by the MAINDAC_PAGE bits in

0x0

R/W

Disabled (does not clock the calibration frequency

accumulator).

Enables (turns on the clock to the calibration

frequency accumulator).

DDSM_EN_CAL_

DC_INPUT

Enable dc input to calibration DDS. This control

is paged by the MAINDAC_PAGE bits in Register

0x008.

0x0

R/W

Mux in datapath signal to the input of the final DDS.

Mux in dc to the input of the final DDS.

DDSM_EN_CAL_

FREQ_TUNE

Enable tuning of the signal to calibration frequency

for DAC0 only. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0

R/W

Disable calibration frequency tuning.

Enable calibration frequency tuning.

0x1E7

DATAPATH_NCO_

[7:2]

RESERVED

Reserved.

0x0

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