AD9173 datasheet(105/144 Pages) AD

105 / 144 page

Data Sheet

AD9173

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Rev. C | 105 of 144

Table 60. Register Details

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

SYNC_CFG

ALL_NCO_SYNC_

ACK

Acknowledge signal that all the active NCOs are

loaded. This bit is the acknowledge indicator for both

the START_NCO_SYNC bit (Bit 0 of this register) and

the NCORST_AFTER_ROT_EN bit (Register 0x03B,

Bit 4) method of resetting the NCOs. This control

is paged by the MAINDAC_PAGE bits in Register

0x008.

0x0

START_NCO_SYNC

Used to start the sync of the NCOs on a rising edge

of the SPI bit or SYSREF± signal, depending on

which is chosen as the update trigger. Upon receiving

a trigger, the FTWs are loaded first, and then a

synchronization occurs. This control is paged by the

MAINDAC_PAGE bits in Register 0x008.

0x0

R/W

0x200

MASTER_PD

[7:1]

RESERVED

Reserved.

0x0

SERDES_MASTER_PD

Powers down the entire JESD204B Rx analog (all

eight channels and bias).

0x1

R/W

0x201

PHY_PD

[7:0]

PHY_PD

SPI override to power down the individual PHYs. Bit 0

controls the SERDIN0± PHY.

0xEE

R/W

Bit 1 controls the SERDIN1± PHY.

Bit 2 controls the SERDIN2± PHY.

Bit 3 controls the SERDIN3± PHY.

Bit 4 controls the SERDIN4± PHY.

Bit 5 controls the SERDIN5± PHY.

Bit 6 controls the SERDIN6± PHY.

Bit 7 controls the SERDIN7± PHY.

0x203

GENERIC_PD

[7:2]

RESERVED

Reserved.

0x0

PD_SYNCOUT0

Powers down the SYNCOUT0± driver.

0x0

R/W

Enables the SYNCOUT0± output pins.

Powers down the SYNCOUT0± output pins.

PD_SYNCOUT1

Powers down the SYNCOUT1± driver.

0x1

R/W

Enables the SYNCOUT1± output pins.

Powers down the SYNCOUT1± output pins.

0x206

CDR_RESET

[7:1]

RESERVED

Reserved.

0x0

CDR_PHY_RESET

PHY reset control bit. Set this bit to 1 to take the

PHYs out of reset during device operation.

0x0

R/W

0x210

CBUS_ADDR

[7:0]

SERDES_CBUS_

ADDR

SERDES configuration control register to set

SERDES configuration address controls.

0x0

R/W

0x212

CBUS_WRSTROBE_

PHY

[7:0]

SERDES_CBUS_

WR0

SERDES configuration control register to commit the

SERDES configuration controls written.

0x0

R/W

0x213

CBUS_WRSTROBE_

[7:1]

RESERVED

Reserved.

0x0

OTHER

SERDES_CBUS_

WR1

SERDES configuration control register to commit the

SERDES configuration controls written.

0x0

R/W

0x216

CBUS_WDATA

[7:0]

SERDES_CBUS_

DATA

SERDES configuration control register to set the

SERDES configuration control data.

0x0

R/W

0x240

EQ_BOOST_PHY_3_0

[7:6]

EQ_BOOST_PHY3

Equalizer setting for PHY 3 based on insertion loss of

the system.

0x3

R/W

Insertion loss ≤ 11 dB.

Insertion loss > 11 dB.

[5:4]

EQ_BOOST_PHY2

Equalizer setting for PHY 2 based on insertion loss of

the system.

0x3

R/W

Insertion loss ≤ 11 dB.

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