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AD9173 Datasheet(PDF) 108 Page - Analog Devices |
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AD9173 Datasheet(HTML) 108 Page - Analog Devices |
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108 / 144 page  Data Sheet AD9173 REGISTER DETAILS analog.com Rev. C | 108 of 144 Table 60. Register Details Addr. Name Bits Bit Name Settings Description Reset Access 1 SYNCOUT0± is set to LVDS output. 0x254 SYNCOUT1_CTRL [7:1] RESERVED Reserved. 0x0 R/W 0 SEL_SYNCOUT1_ MODE This control determines the output driver mode for the SYNCOUT1± pin operation. Both SYNCOUT0± and SYNCOUT1± must be set to the same mode of operation. 0x0 R/W 0 SYNCOUT1± is set to CMOS output. 1 SYNCOUT1± is set to LVDS output. 0x280 PLL_ENABLE_CTRL [7:3] RESERVED Reserved. 0x0 R 2 LOLSTICKYCLEAR_LC PLL_RC Clears out loss of lock bit. 0x0 R/W 1 LDSYNTH_LCPLL_RC Pulse high to start VCO calibration (without restarting the regulator or remeasuring the temperature). 0x0 R/W 0 SERDES_PLL_ STARTUP SERDES circuitry blocks are powered off when this bit is set to 0. Set this bit to 1 at the end of the SERDES configuration writes. When this bit is set to 1, it powers up the SERDES PLL blocks and starts the LDO and calibration routine to lock the PLL auto-matically to the appropriate lane rate based on the JESD204B mode and interpolation options programmed in the device. The SERDES_PLL_LOCK bit (Register 0x281, Bit 0) reads 1 when the PLL achieves lock. 0x1 R/W 0x281 PLL_STATUS [7:1] RESERVED Reserved. 0x0 R 0 SERDES_PLL_LOCK PLL is locked when this bit is high. 0x0 R 0x300 GENERAL_JRX_ [7:4] RESERVED Reserved. 0x0 R CTRL_0 3 LINK_MODE Reads back 0 when in single-link mode and 1 when in dual-link mode. 0x0 R/W 2 LINK_PAGE Link paging. This bit selects which link register map is used. This paging affects Register 0x400 to Register 0x4BB. 0x0 R/W 0 Page QBD0 for Link 0. 1 Page QBD1 for Link 1. [1:0] LINK_EN These bits bring up the JESD204B digital Rx when all link parameters are programmed and all clocks are ready. Bit 0 applies to Link 0, whereas Bit 1 applies to Link 1. Link 1 is only available in dual-link mode. 0x0 R/W 0x302 DYN_LINK_ [7:6] RESERVED Reserved. 0x0 R LATENCY_0 [5:0] DYN_LINK_ LATENCY_0 Dynamic link latency, Link 0. Latency between the LMFC Rx for Link 0 and the last arriving LMFC boundary in units of PCLK cycles. 0x0 R 0x303 DYN_LINK_ [7:6] RESERVED Reserved. 0x0 R LATENCY_1 [5:0] DYN_LINK_ LATENCY_1 Dynamic link latency, Link 1. Latency between the LMFC Rx for Link 1 and the last arriving LMFC boundary in units of PCLK cycles. 0x0 R 0x304 LMFC_DELAY_0 [7:6] RESERVED Reserved. 0x0 R [5:0] LMFC_DELAY_0 LMFC delay, Link 0. Delay from the LMFC to the LMFC Rx for Link 0 in units of PCLK cycles. 0x0 R/W 0x305 LMFC_DELAY_1 [7:6] RESERVED Reserved. 0x0 R [5:0] LMFC_DELAY_1 LMFC delay, Link 1. Delay from the LMFC to the LMFC Rx for Link 1 in units of PCLK cycles. 0x0 R/W 0x306 LMFC_VAR_0 [7:6] RESERVED Reserved. 0x0 R |
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