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AD9173 Datasheet(PDF) 107 Page - Analog Devices

Part # AD9173
Description  Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9173 Datasheet(HTML) 107 Page - Analog Devices

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Data Sheet
AD9173
REGISTER DETAILS
analog.com
Rev. C | 107 of 144
Table 60. Register Details
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
[5:4]
EQ_GAIN_PHY6
Equalizer gain for PHY 6 based on insertion loss of
the system.
0x3
R/W
01
Insertion loss ≤ 11 dB.
11
Insertion loss > 11 dB.
[3:2]
EQ_GAIN_PHY5
Equalizer gain for PHY 5 based on insertion loss of
the system.
0x3
R/W
01
Insertion loss ≤ 11 dB.
11
Insertion loss > 11 dB.
[1:0]
EQ_GAIN_PHY4
Equalizer gain for PHY 4 based on insertion loss of
the system.
0x3
R/W
01
Insertion loss ≤ 11 dB.
11
Insertion loss > 11 dB.
0x244
EQ_FB_PHY_0
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
EQ_PHY_0
SERDES equalizer setting for PHY0. Set this control
to 0x1F for optimal performance.
0x19
R/W
0x245
EQ_FB_PHY_1
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
EQ_PHY1
SERDES equalizer setting for PHY1. Set this control
to 0x1F for optimal performance.
0x19
R/W
0x246
EQ_FB_PHY_2
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
EQ_PHY2
SERDES equalizer setting for PHY2. Set this control
to 0x1F for optimal performance.
0x19
R/W
0x247
EQ_FB_PHY_3
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
EQ_PHY3
SERDES equalizer setting for PHY3. Set this control
to 0x1F for optimal performance.
0x19
R/W
0x248
EQ_FB_PHY_4
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
EQ_PHY4
SERDES equalizer setting for PHY4. Set this control
to 0x1F for optimal performance.
0x19
R/W
0x249
EQ_FB_PHY_5
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
EQ_PHY5
SERDES equalizer setting for PHY5. Set this control
to 0x1F for optimal performance.
0x19
R/W
0x24A
EQ_FB_PHY_6
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
EQ_PHY6
SERDES equalizer setting for PHY6. Set this control
to 0x1F for optimal performance.
0x19
R/W
0x24B
EQ_FB_PHY_7
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
EQ_PHY7
SERDES equalizer setting for PHY7. Set this control
to 0x1F for optimal performance.
0x19
R/W
0x250
LBT_REG_CNTRL_0
[7:0]
EN_LBT_DES_RC_CH
Enable loopback test for desired physical lanes per
PHY, with Bit x corresponding to PHY x.
0x0
R/W
0x251
LBT_REG_CNTRL_1
[7:2]
RESERVED
Reserved.
0x0
R
1
EN_LBT_
HALFRATE_DES_RC
Enables half rate mode for the loopback test. If this bit
is set to 1, the output data rate = 2× the input clock
frequency. If this bit is set to 0, the output data rate =
the input clock frequency.
0x1
R/W
0
INIT_LBT_SYNC_
DES_RC
Initiate the loopback test by toggling this bit from 0 to
1, then back to 0.
0x0
R/W
0x253
SYNCOUT0_CTRL
[7:1]
RESERVED
Reserved.
0x0
R/W
0
SEL_SYNCOUT0_
MODE
This control determines the output driver mode for
the SYNCOUT0± pin operation. Both SYNCOUT0±
and SYNCOUT1± must be set to the same mode of
operation.
0x0
R/W
0
SYNCOUT0± is set to CMOS output.



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