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AD9559

Data Sheet

Rev. 0 | Page 34 of 120

DIGITAL PLL (DPLL) CORE

DPLL Overview

Diagrams of the DPLL cores of the AD9559 (DPLL_0 and

DPLL_1) are shown in Figure 35 and Figure 36, respectively.

The blocks shown in these diagrams are purely digital.

The start of the DPLL signal chain is the reference signal, fR,

which has been divided by the R divider and then routed through

the crosspoint switch to the DPLL. The frequency of this signal,

fTDC, is:

TDC

This is the frequency used by the time-to-digital converter,

TDC, inside the DPLL.

A TDC samples the output of the R divider. The TDC/PFD

produces a time series of digital words and delivers them to the

digital loop filter. The digital loop filter offers the following:

•

The determination of the filter response by numeric

coefficients rather than by discrete component values

•

The absence of analog components (R/L/C), which

eliminates tolerance variations due to aging

•

The absence of thermal noise associated with analog

components

•

The absence of control node leakage current associated

with analog components (a source of reference feed-

through spurs in the output spectrum of a traditional APLL)

The digital loop filter produces a time series of digital words at

its output and delivers them to the frequency tuning input of a

sigma-delta (Σ-Δ) modulator. The digital words from the loop

filter steer the SDM frequency toward frequency and phase lock

with the input signal (fTDC).

Each DPLL includes a feedback divider that causes the digital

loop to operate at an integer-plus-fractional multiple. The

output of the DPLL is









MOD

FRAC

TDC

DPLL

OUT

)

(

where N is the 17-bit value stored in the appropriate profile

registers (Register 0x0440 to Register 0x044C for DPLL_0

REFA). FRAC and MOD are the 24-bit numerators and

denominators of the fractional feedback divider block. The

fractional portion of the feedback divider can be bypassed by

setting FRAC to 0. MOD can be set to 0, but never change MOD

from 0 to nonzero without first entering free run mode.

Note that there are two DPLLs. In the Register Map and Register

Map Bit Descriptions sections, N0, FRAC0, and MOD0 are used

for DPLL_0; N1, FRAC1, and MOD1 are used for DPLL_1.

For optimal performance, the DPLL output frequency is typically

175 MHz to 200 MHz.

TDC/PFD

The phase frequency detector (PFD) is an all-digital block. It

compares the digital output from the TDC (which relates to the

active reference edge) with the digital word from the feedback

block. It uses a digital code pump and digital integrator (rather

than a conventional charge pump and capacitor) to generate the

error signal that steers the SDM frequency toward phase lock.

DIGITAL

LOOP

FILTER

÷N0

24-BIT/24-BIT

RESOLUTION

FRAC0/

MOD0

17-BIT

INTEGER

TUNING

WORD

CLAMP

AND

HISTORY

×2

FREE RUN

SYSTEM

CLOCK

FROM APLL_0

TO APLL_0

R DIVIDER

(20-BIT)

REF

INPUT

MUX

REF

INPUT

Figure 35. DPLL_0 Core

DIGITAL

LOOP

FILTER

÷N1

24-BIT/24-BIT

RESOLUTION

FRAC1/

MOD1

17-BIT

INTEGER

TUNING

WORD

CLAMP

AND

HISTORY

×2

FREE RUN

SYSTEM

CLOCK

FROM APLL_1

TO APLL_1

R DIVIDER

(20-BIT)

REF

INPUT

MUX

REF

INPUT

Figure 36. DPLL_1 Core

AD9559PCBZ Datasheet(PDF) 34 Page - Analog Devices

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