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AD9559PCBZ Datasheet(PDF) 17 Page - Analog Devices |
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AD9559PCBZ Datasheet(HTML) 17 Page - Analog Devices |
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17 / 120 page  Data Sheet AD9559 Rev. 0 | Page 17 of 120 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD3 REFA REFA VDD VDD GND VDD VDD VDD LDO_0 LF_0 VDD3 VDD VDD OUT0A OUT0A 17 VDD 18 VDD3 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VDD3 REFC REFC VDD VDD GND VDD VDD VDD LDO_1 LF_1 VDD3 VDD VDD OUT1A OUT1A VDD VDD3 PIN 1 INDICATOR AD9559 TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. Figure 2. Pin Configuration Table 21. Pin Function Descriptions Pin No. Mnemonic Input/ Output Pin Type Description 1, 12, 18, 28, 37, 43, 54, 55, 72 VDD3 I Power 3.3 V Power Supply. See the Power Supply Partitions section for information about the recommended grouping of the power supply pins. 2 REFA I Differential input Reference A Input. This internally biased input is typically ac-coupled; when configured in this manner, it can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS. 3 A REFAE I Differential input Complementary Reference A Input. Complementary signal to the input provided on Pin 2. 4, 5, 7, 8, 9, 13, 14, 17, 21, 34, 38, 41, 42, 46, 47, 48, 50, 51, 58, 59, 60, 61, 62, 65, 66, 67, 68, 69 VDD I Power 1.8 V Power Supply. See the Power Supply Partitions section for information about the recommended grouping of the power supply pins. Note that, for Pin 34 and Pin 21, it is recommended that a Size 0201, 0.1 µF bypass capacitor be placed between Pin 33 and Pin 34, as well as between Pin 21 and Pin 22, as close as possible to the AD9559. 6, 22, 33, 49 GND O Ground Connect these pins (along with the exposed die pad) to ground. 10 LDO_0 I LDO bypass Output PLL0 Loop Filter Voltage Regulator. Connect a 0.47 μF capacitor from this pin to ground. This pin is also the ac ground reference for the integrated output PLL external loop filter. 11 LF_0 I/O Loop filter for APLL_0 Loop Filter Node for the Output PLL0. Connect an external 6.8 nF capacitor from this pin to Pin 10 (LDO_0). 15 A OUT0AE O HSTL, LVDS, 1.8 V CMOS PLL0 Complementary Output 0A. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. 16 OUT0A O HSTL, LVDS, 1.8 V CMOS PLL0 Output 0A. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. LVPECL levels can be achieved by ac-coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section. |
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