AD9559PCBZ datasheet(77/120 Pages) AD

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Data Sheet

AD9559

Rev. 0 | Page 77 of 120

REFERENCE INPUT A (REGISTER 0x0300 TO REGISTER 0x031A)

Table 49. REFA Logic Type

Address

Bits

Bit Name

Description

0x0300

[7:4]

Reserved

Default: 0x0

Enable REFA divide-by-2

Enables the reference input divide-by-2 for REFA

0 = bypasses the divide-by-2 (default)

1 = enables the divide-by-2

Reserved

Default: 0b

[1:0]

REFA logic type

Selects logic family for REFA input receiver; only the REFA pin is used in CMOS mode

00 (default) = differential

01 = 1.2 V to 1.5 V CMOS

10 = 1.8 V to 2.5 V CMOS

11 = 3.0 V to 3.3 V CMOS

Table 50. REFA 20-Bit DPLL R Divider

Address

Bits

Bit Name

Description

0x0301

[7:0]

R divider

DPLL integer reference divider (minus 1), Bits[7:0] (default: 0xCF)

0x0302

[7:0]

DPLL integer reference divider (minus 1), Bits[15:8] (default: 0x00)

0x0303

[7:4]

Reserved

Default: 0x0

[3:0]

R divider

DPLL integer reference divider (minus 1), Bits[19:16] (default: 0x0)

Table 51. Nominal Period of REFA Input Clock

Address

Bits

Bit Name

Description

0x0304

[7:0]

REFA nominal

reference period (fs)

Nominal reference period, Bits[7:0] (default: 0xC9)

0x0305

[7:0]

Nominal reference period, Bits[15:8] (default: 0xEA)

0x0306

[7:0]

Nominal reference period, Bits[23:16] (default: 0x10)

0x0307

[7:0]

Nominal reference period, Bits[31:24] (default: 0x03)

0x0308

[7:0]

Nominal reference period, Bits[39:32] (default: 0x00)

Default for Register 0x0304 to Register 0x0308: 0x000310EAC9 = 51.44 ns (1/19.44 MHz).

Table 52. REFA Frequency Tolerance

Address

Bits

Bit Name

Description

0x0309

[7:0]

Inner tolerance

Input reference frequency monitor inner tolerance, Bits[7:0] (default: 0x14).

0x030A

[7:0]

Input reference frequency monitor inner tolerance, Bits[15:8] (default: 0x00).

0x030B

[7:4]

Reserved

Default: 0x0.

[3:0]

Inner tolerance

Input reference frequency monitor inner tolerance, Bits[19:16].

Default for Register 0x0309 to Register 0x30B: 0x000014 = 20 (5% or 50,000 ppm).

The Stratum 3 clock requires inner tolerance of ±9.2 ppm and outer tolerance of ±12 ppm;

an SMC clock requires outer tolerance of ±48 ppm.

The allowable range for the inner tolerance is 0x00A (10%) to 0x8FF (2 ppm).

0x030C

[7:0]

Outer tolerance

Input reference frequency monitor outer tolerance, Bits[7:0] (default: 0x0A).

0x030D

[7:0]

Input reference frequency monitor outer tolerance, Bits[15:8] (default: 0x00).

0x030E

[7:4]

Reserved

Default: 0x0.

[3:0]

Outer tolerance

Input reference frequency monitor outer tolerance, Bits[19:16].

Default for Register 0x030C to Register 0x30E = 0x00000A = 10 (10% or 100,000 ppm).

The Stratum 3 clock requires inner tolerance of ±9.2 ppm and outer tolerance of ±12 ppm;

an SMC clock requires outer tolerance of ±48 ppm. The outer tolerance must be greater than

the inner tolerance so that there is hysteresis.

AD9559PCBZ Datasheet(PDF) 77 Page - Analog Devices

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