AD9559PCBZ datasheet(95/120 Pages) AD

95 / 120 page

Data Sheet

AD9559

Rev. 0 | Page 95 of 120

Table 119. Distribution OUT1A Settings

Address

Bits

Bit Name

Description

0x0527

Reserved

Default: 0b.

[6:4]

OUT1A format

Select the operating mode of OUT1A.

000 = power-down, tristate.

001 (default) = HSTL.

010 = LVDS.

011 = reserved.

100 = CMOS, both outputs active.

101 = CMOS, P output active, N output power-down.

110 = CMOS, N output active, P output power-down.

111 = reserved.

[3:2]

OUT1A polarity

Control the OUT1A polarity.

00 (default) = positive, negative.

01 = positive, positive.

10 = negative, positive.

11 = negative, negative.

OUT1A LVDS boost

Controls the output drive capability of OUT1A.

0 (default) = LVDS: 3.5 mA drive strength.

1 = LVDS: 4.5 mA drive strength (LVDS boost mode).

Reserved

Default: 0b.

Table 120. Q1_A Divider Settings

Address

Bits

Bit Name

Description

0x0528

[7:0]

Q1_A divider

10-bit channel divider, Bits[7:0] (LSB).

Division equals channel divider, Bits[9:0] + 1.

([9:0] = 0 is divide-by-1, [9:0] = 1 is divide-by-2…[9:0] = 1023 is divide-by-1024).

0x0529

[7:2]

Reserved

Reserved.

[1:0]

Q1_A divider

10-bit channel divider, Bits[9:8] (MSB), Bits[1:0].

0x052A

[7:6]

Reserved

Reserved.

[5:0]

Q1_A divider phase

Divider initial phase after sync relative to the divider input clock (from the P1 divider output).

LSB is ½ of a period of the divider input clock.

Phase = 0 is no phase offset.

Phase = 1 is ½ a period offset.

Table 121. Distribution OUT1B Settings

Address

Bits

Bit Name

Description

0x052B

Enable 3.3 V CMOS driver

0 (default) = disables 3.3 V CMOS driver, and OUT1B logic is controlled by 0x052B[6:4].

1 = enables 3.3 V CMOS driver as operating mode of OUT1.

This bit should be enabled only if Bits[6:4] are in CMOS mode.

[6:4]

OUT1B format

Select the operating mode of OUT1B.

000 = power-down, tristate.

001 = HSTL.

010 = LVDS.

011 = reserved.

100 = CMOS, both outputs active.

101 = CMOS, P output active, N output power-down.

110 = CMOS, N output active, P output power-down.

111 = reserved.

[3:2]

OUT1B polarity

Configure the OUT1B polarity in CMOS mode. These bits are active in CMOS mode only.

00 (default) = positive, negative.

01 = positive, positive.

10 = negative, positive.

11 = negative, negative.

OUT1B LVDS boost

Controls the output drive capability of OUT1B.

0 (default) = LVDS: 3.5 mA drive strength.

1 = LVDS: 4.5 mA drive strength (LVDS boost mode).

Reserved

Default: 0b.

AD9559PCBZ Datasheet(PDF) 95 Page - Analog Devices

AD9559PCBZ Datasheet(HTML) 95 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL