AD9559PCBZ datasheet(18/120 Pages) AD

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AD9559

Data Sheet

Rev. 0 | Page 18 of 120

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

OUT0BE

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

PLL0 Complementary Output 0B. This output can be configured as HSTL, LVDS,

or single-ended 1.8 V or 3.3 V CMOS.

OUT0B

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

PLL0 Output 0B. This output can be configured as HSTL, LVDS, or single-ended 1.8 V

or 3.3 V CMOS. LVPECL levels can be achieved by ac-coupling and using the

Thevenin-equivalent termination as described in the Input/Output Termination

Recommendations section.

RESETE

3.3 V CMOS

Logic

Chip Reset. When this active low pin is asserted, the chip goes into reset. This pin

has an internal 50 kΩ pull-up resistor.

SCLK/SCL

3.3 V CMOS

Serial Programming Clock in SPI Mode (SCLK). Data clock for serial programming.

Serial Clock Pin in I2C Mode (SCL).

SDIO/SDA

I/O

3.3 V CMOS

Serial Data Input/Output (SDIO). When the device is in 4-wire SPI mode, data is

written via this pin. In 3-wire SPI mode, data reads and writes both occur on this

pin. There is no internal pull-up/pull-down resistor on this pin.

Serial Data Pin in I2C Mode (SDA).

M5/

CSE

I/O

3.3 V CMOS

Configurable I/O Pin (M5). Used for status and control of the AD9559.

Chip Select in SPI Mode (

CSE

). Active low input. When programming a device in

SPI, this pin must be held low. In systems where more than one AD9559 is present,

this pin enables individual programming of each AD9559. This pin has an internal

10 kΩ pull-up resistor.

M4/SDO

I/O

3.3 V CMOS

Configurable I/O Pin (M4). Used for status and control of the AD9559.

Serial Data Output (SDO). In 4-wire SPI mode, this pin is used for reading serial data.

29, 30, 31, 32

M3, M2, M1,

I/O

3.3 V CMOS

Configurable I/O Pins. These pins are used for status and control of the AD9559.

These pins are also used at power-up and reset to control the serial port configuration

and EEPROM loading. See Table 23 and Table 25 for more information. These pins

do NOT have internal pull-down resistors.

OUT1B

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

PLL1 Output 1B. This output can be configured as HSTL, LVDS, or single-ended 1.8 V

or 3.3 V CMOS. LVPECL levels can be achieved by ac-coupling and using the

Thevenin-equivalent termination as described in the Input/Output Termination

Recommendations section.

OUT1BE

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

PLL1 Complementary Output 1B. This output can be configured as HSTL, LVDS,

or single-ended 1.8 V or 3.3 V CMOS.

OUT1A

HSTL, LVDS,

1.8 V CMOS

PLL1 Output 1A. This output can be configured as HSTL, LVDS, or single-ended

1.8 V CMOS. LVPECL levels can be achieved by ac-coupling and using the

Thevenin-equivalent termination as described in the Input/Output Termination

Recommendations section.

OUT1AE

HSTL, LVDS,

1.8 V CMOS

PLL1 Complementary Output 1A. This output can be configured as HSTL, LVDS, or

single-ended 1.8 V CMOS.

LF_1

I/O

Loop filter for

APLL_1

Loop Filter Node for the Output PLL1. Connect an external 6.8 nF capacitor from

this pin to Pin 45 (LDO_1).

LDO_1

LDO bypass

Output PLL1 Loop Filter Voltage Regulator. Connect a 0.47 μF capacitor from this

pin to ground. This pin is also the ac ground reference for the integrated output

PLL external loop filter.

REFCE

Differential

input

Complementary Reference C Input. Complementary signal to the input provided

on Pin 53.

REFC

Differential

input

Reference C Input. This internally biased input is typically ac-coupled; when

configured in that manner, it can accept any differential signal with single-ended

swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended

CMOS.

REFDE

Differential

input

Complementary Reference D Input. Complementary signal to the input provided

on Pin 57.

REFD

Differential

input

Reference D Input. This internally biased input is typically ac-coupled; when

configured in this manner, it can accept any differential signal with single-ended

swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

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