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AD9559PCBZ Datasheet(PDF) 93 Page - Analog Devices

Part # AD9559PCBZ
Description  Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
PDF  120 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9559PCBZ Datasheet(HTML) 93 Page - Analog Devices

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Data Sheet
AD9559
Rev. 0 | Page 93 of 120
APLL_1 CONFIGURATION (REGISTER 0x0520 TO REGISTER 0x0523)
Table 116. Output PLL_1 (APLL_1) Setting1
Address
Bits
Bit Name
Description
0x0520
[7:0]
APLL_1 charge pump
current
LSB = 3.5 µA
00000001 = 1 × LSB; 00000010 = 2 × LSB; 11111111 = 255 × LSB
Default: 0x81 = 451 µA CP current
0x0521
[7:0]
APLL_1 M1 (feedback)
divider
Division: 14 to 255
Default: 0x14 = divide-by-20
0x0522
[7:6]
APLL_1 loop filter control
Pole 2 resistor, Rp2; default: 0x07
Rp2 (Ω)
Bit 7
Bit 6
500 (default)
0
0
333
0
1
250
1
0
200
1
1
[5:3]
Zero resistor, Rzero.
Rzero (Ω)
Bit 5
Bit 4
Bit 3
1500 (default)
0
0
0
1250
0
0
1
1000
0
1
0
930
0
1
1
1250
1
0
0
1000
1
0
1
750
1
1
0
680
1
1
1
[2:0]
Pole 1, Cp1
Cp1 (pF)
Bit 2
Bit 1
Bit 0
0
0
0
0
20
0
0
1
80
0
1
0
100
0
1
1
20
1
0
0
40
1
0
1
100
1
1
0
120 (default)
1
1
1
0x0523
[7:1]
Reserved
Default: 0x00
0
Bypass internal Rzero
0 (default) = uses the internal Rzero resistor
1 = bypasses the internal Rzero resistor (makes Rzero = 0 and requires the use of a series
external zero resistor in addition to the capacitor to ground on the LF_1 pin)
1
Note that the default APLL loop BW is 240 kHz.



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