AD9559PCBZ datasheet(26/120 Pages) AD

26 / 120 page

AD9559

Data Sheet

Rev. 0 | Page 26 of 120

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

AD9559

HSTL OR

LVDS

DOWNSTREAM

DEVICE

WITH HIGH

IMPEDANCE

INPUT AND

INTERNAL

DC BIAS

0.1µF

100Ω

Z0 = 50Ω

SINGLE-ENDED

(NOT COUPLED)

Figure 29. AC-Coupled LVDS or HSTL Output Driver

(100 Ω resistor can be placed on either side of decoupling capacitors

and should be as close to the destination receiver as possible.)

AD9559

HSTL OR

LVDS

Z0 = 50Ω

SINGLE-ENDED

(NOT COUPLED)

LVDS OR 1.8V HSTL

HIGH IMPEDANCE

DIFFERENTIAL

RECEIVER

100Ω

Figure 30. DC-Coupled LVDS or HSTL Output Driver

SINGLE-ENDED

(NOT COUPLED)

VS = 3.3V

3.3V

LVPECL

82Ω

127Ω

0.1µF

AD9559

1.8V

HSTL

Z0 = 50Ω

Figure 31. Interfacing the HSTL Driver to a 3.3 V LVPECL Input

(This method incorporates impedance matching and dc-biasing for bipolar

LVPECL receivers. If the receiver is self-biased, the termination scheme shown in

Figure 29 is recommended.)

XOA

XOB

AD9559

10MHz TO 50MHz FUNDAMENTAL

AT-CUT CRYSTAL WITH

10pF LOAD CAPACITANCE

10pF

Figure 32. System Clock Input (XOA/XOB) in Crystal Mode

(The recommended CLOAD = 10 pF is shown. The values of 10 pF shunt capacitors

shown here should equal the CLOAD of the crystal.)

XOA

300Ω

150Ω

0.1µF

XOB

AD9559

3.3V

CMOS

TCXO

0.1µF

Figure 33. System Clock Input (XOA, XOB)

When Using a TCXO/OCXO with 3.3 V CMOS Output

AD9559PCBZ Datasheet(PDF) 26 Page - Analog Devices

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