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AD9559

Data Sheet

Rev. 0 | Page 98 of 120

DPLL_1 SETTINGS FOR REFERENCE INPUT A (REFA) (REGISTER 0x055A TO REGISTER 0x0566)

Table 133. DPLL_1 REFA Priority Setting

Address

Bits

Bit Name

Description

0x055A

[7:3]

Reserved

Default: 00000b.

[2:1]

REFA priority

These bits set the priority level (0 to 3) of REFA relative to the other input references.

00 (default) = 0 (highest).

01 = 1.

10 = 2.

11 = 3.

Enable REFA

This bit enables DPLL_1 to lock to REFA.

0 (default) = REFA is not enabled for use by DPLL_1.

1 = REFA is enabled for use by DPLL_1.

Table 134. DPLL_1 REFA Loop BW Scaling Factor

Address

Bits

Bit Name

Description

0x055B

[7:0]

DPLL loop BW scaling factor

(unit of 0.1 Hz)

Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4).

0x055C

[7:0]

Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01).

The default for Register 0x055B and Register 0x0555C = 0x01F4 = 500 (50 Hz loop BW).

The loop bandwidth should always be less than the DPLL phase detector frequency divided

by 20. The DPLL may not lock reliably if the DPLL loop BW is <50 Hz and a crystal is used

for the system clock. See the Choosing the SYSCLK Source section for details.

0x055D

[7:2]

Reserved

Default: 0x00.

Base loop filter selection

0 = base loop filter with normal (70°) phase margin (default).

1 = base loop filter with high phase margin.

(≤0.1 dB peaking in the closed-loop transfer function for loop BW ≤ 2 kHz. Setting this bit

is also recommended for loop BW > 2 kHz.)

Reserved

Default: 0b.

Table 135. DPLL_1 REFA Integer Part of Feedback Divider

Address

Bits

Bit Name

Description

0x055E

[7:0]

Integer Part N1

DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0xCB).

0x055F

[7:0]

DPLL integer feedback divider, Bits[15:8] (default: 0x07).

0x0560

[7:1]

Reserved

Default: 0x00.

Integer Part N1

DPLL integer feedback divider, Bit 16 (default: 0b).

The default for Register 0x055E to Register 0x0560: 0x007CB (which equals N1 = 1996).

Table 136. DPLL_1 REFA Fractional Part of Fractional Feedback Divider FRAC1

Address

Bits

Bit Name

Description

0x0561

[7:0]

Digital PLL fractional

feedback divider—FRAC1

The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04)

0x0562

[7:0]

The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)

0x0563

[7:0]

The numerator of the fractional-N feedback divider, Bits[23:18] (default: 0x00)

Table 137. DPLL_1 REFA Modulus of Fractional Feedback Divider MOD1

Address

Bits

Bit Name

Description

0x0564

[7:0]

Digital PLL feedback divider

modulus—MOD1

The denominator of the fractional-N feedback divider, Bits[7:0] (default: 0x05)

0x0565

[7:0]

The denominator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)

0x0566

[7:0]

The denominator of the fractional-N feedback divider, Bits[23:17] (default: 0x00)

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