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AD9559PCBZ Datasheet(PDF) 62 Page - Analog Devices |
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AD9559PCBZ Datasheet(HTML) 62 Page - Analog Devices |
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62 / 120 page  AD9559 Data Sheet Rev. 0 | Page 62 of 120 Reg Addr (Hex) Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) 0x036F W0 REFD validation Validation timer (ms), Bits[7:0] (up to 65.5 sec) 0x0A 0x0370 W0 Validation timer (ms), Bits[15:8] (up to 65.5 sec) 0x00 0x0371 W1 REFD phase lock detector Phase lock threshold (ps), Bits[7:0] 0xBC 0x0372 W1 Phase lock threshold (ps), Bits[15:8] 0x02 0x0373 W1 Phase lock threshold (ps), Bits [23:16] 0x00 0x0374 W1 Phase lock fill rate, Bits[7:0] 0x0A 0x0375 W1 Phase lock drain rate, Bits[7:0] 0x0A 0x0376 W1 REFD frequency lock detector Frequency lock threshold, Bits[7:0] 0xBC 0x0377 W1 Frequency lock threshold, Bits[15:8] 0x02 0x0378 W1 Frequency lock threshold, Bits[23:16] 0x00 0x0379 W1 Frequency lock fill rate, Bits[7:0] 0x0A 0x037A W1 Frequency lock drain rate, Bits[7:0] 0x0A DPLL_0 General Settings 0x0400 DPLL_0 free run frequency TW 30-bit free running frequency tuning word, Bits[7:0] 0x12 0x0401 30-bit free running frequency tuning word, Bits[15:8] 0x15 0x0402 30-bit free running frequency tuning word, Bits[23:16] 0x64 0x0403 Reserved 30-bit free running frequency tuning word, Bits[29:24] 0x1B 0x0404 DCO_0 control Reserved Digital oscillator SDM integer part, Bits[3:0] 0x08 0x0405 DPLL_0 frequency clamp Lower limit of pull-in range, Bits[7:0] 0x51 0x0406 Lower limit of pull-in range, Bits[15:8] 0xB8 0x0407 Reserved Lower limit of pull-in range, Bits[19:16] 0x02 0x0408 Upper limit of pull-in range, Bits[7:0] 0x3E 0x0409 Upper limit of pull-in range, Bits[15:8] 0x0A 0x040A Reserved Upper limit of pull-in range, Bits[19:16] 0x0B 0x040B DPLL_0 holdover history History accumulation timer (ms), Bits[7:0] (up to 65 sec) 0x0A 0x040C History accumulation timer (ms), Bits[15:8] (up to 65 sec) 0x00 0x040D DPLL_0 history mode Reserved Single sample fallback Persistent history Incremental average 0x00 0x040E DPLL_0 closed loop phase offset (±0.5 ms) Fixed phase offset (signed; ps), Bits[7:0] 0x00 0x040F Fixed phase offset (signed; ps), Bits[15:8] 0x00 0x0410 Fixed phase offset (signed; ps), Bits[23:16] 0x00 0x0411 Reserved Fixed phase offset (signed; ps), Bits[29:24] 0x00 0x0412 Incremental phase offset step size (ps/step), Bits[7:0] (up to 65.5 ns/step) 0x00 0x0413 Incremental phase offset step size (ps/step), Bits[15:8] (up to 65.5 ns/step) 0x00 0x0414 DPLL_0 phase slew limit Phase slew rate limit (µs/sec), Bits[7:0] (315 µs/sec up to 65.536 ms/sec) 0x00 0x0415 Phase slew rate Limit (µs/sec), Bits[15:8] (315 µs/sec up to 65.536 ms/sec) 0x00 Output PLL_0 (APLL_0) and Channel 0 Output Drivers 0x0420 APLL_0 charge pump Output PLL0 (APLL_0) charge pump current, Bits[7:0] 0x81 0x0421 APLL_0 M0 divider Output PLL0 (APLL_0) feedback (M0) divider, Bits[7:0] 0x14 0x0422 APLL_0 loop filter control APLL_0 loop filter control, Bits[7:0] 0x07 0x0423 Reserved Bypass internal Rzero 0x00 0x0424 P0 divider Reserved P0 divider divide ratio, Bits[3:0] 0x04 0x0425 OUT0 sync Reserved Sync source selection Auto sync mode 0x00 0x0426 Reserved APLL_0 locked controlled sync disable Mask OUT0B sync Mask OUT0A sync 0x00 |
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