AD9559PCBZ datasheet(78/120 Pages) AD

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AD9559

Data Sheet

Rev. 0 | Page 78 of 120

Table 53. REFA Validation Timer

Address

Bits

Bit Name

Description

0x030F

[7:0]

Validation timer (ms)

Validation timer, Bits[7:0] (default: 0x0A).

This is the amount of time a reference input must be valid before it is declared valid by the

reference input monitor (default: 10 ms).

0x0310

[7:0]

Validation timer, Bits[15:8] (default: 0x00).

Table 54. REFA Lock Detectors

Address

Bits

Bit Name

Description

0x0311

[7:0]

Phase lock threshold

Phase lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps

0x0312

[7:0]

Phase lock threshold, Bits[15:8] (default: 0x02)

0x0313

[7:0]

Phase lock threshold, Bits[23:16] (default: 0x00)

0x0314

[7:0]

Phase lock fill rate

Phase lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)

0x0315

[7:0]

Phase lock drain rate

Phase lock drain rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)

0x0316

[7:0]

Frequency lock threshold

Frequency lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps

0x0317

[7:0]

Frequency lock threshold, Bits[15:8] (default: 0x02)

0x0318

[7:0]

Frequency lock threshold, Bits[23:16] (default: 0x00)

0x0319

[7:0]

Frequency lock fill rate

Frequency lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)

0x031A

[7:0]

Frequency lock drain rate

Frequency lock drain rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)

REFERENCE INPUT B (REGISTER 0x0320 TO REGISTER 0x033A)

Table 55. REFB Logic Type

Address

Bits

Bit Name

Description

0x0320

[7:4]

Reserved

Default: 0x0

Enable REFB divide-by-2

Enables the reference input divide-by-2 for REFB

0 = bypasses the divide-by-2 (default)

1 = enables the divide-by-2

Reserved

Default: 0b

[1:0]

REFB logic type

Selects logic family for REFB input receiver; only the REFB pin is used in CMOS mode

00 (default) = differential

01 = 1.2 V to 1.5 V CMOS

10 = 1.8 V to 2.5 V CMOS

11 = 3.0 V to 3.3 V CMOS

Table 56. REFB 20-Bit DPLL R Divider

Address

Bits

Bit Name

Description

0x0321

[7:0]

R divider

DPLL integer reference divider (minus 1), Bits[7:0] (default: 0xCF)

0x0322

[7:0]

DPLL integer reference divider (minus 1), Bits[15:8] (default: 0x00)

0x0323

[7:4]

Reserved

Default: 0x0

[3:0]

R divider

DPLL integer reference divider (minus 1), Bits[19:16] (default: 0x0)

Table 57. Nominal Period of REFB Input Clock

Address

Bits

Bit Name

Description

0x0324

[7:0]

REFB nominal

reference period (fs)

Nominal reference period, Bits[7:0] (default: 0xC9).

0x0325

[7:0]

Nominal reference period, Bits[15:8] (default: 0xEA).

0x0326

[7:0]

Nominal reference period, Bits[23:16] (default: 0x10).

0x0327

[7:0]

Nominal reference period, Bits[31:24] (default: 0x03).

0x0328

[7:0]

Nominal reference period, Bits[39:32] (default: 0x00).

Default for Register 0x0324 to Register 0x0328: 0x000310EAC9 = 51.44 ns (1/19.44 MHz).

AD9559PCBZ Datasheet(PDF) 78 Page - Analog Devices

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