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AD9559PCBZ Datasheet(PDF) 82 Page - Analog Devices |
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AD9559PCBZ Datasheet(HTML) 82 Page - Analog Devices |
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82 / 120 page  AD9559 Data Sheet Rev. 0 | Page 82 of 120 Table 72. REFD Lock Detectors Address Bits Bit Name Description 0x0371 [7:0] Phase lock threshold Phase lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps 0x0372 [7:0] Phase lock threshold, Bits[15:8] (default: 0x02) 0x0373 [7:0] Phase lock threshold, Bits[23:16] (default: 0x00) 0x0374 [7:0] Phase lock fill rate Phase lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle) 0x0375 [7:0] Phase lock drain rate Phase lock drain rate, Bits[7:0] (default: 0x0A=10 code/PFD cycle) 0x0376 [7:0] Frequency lock threshold Frequency lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps 0x0377 [7:0] Frequency lock threshold, Bits[15:8] (default: 0x02) 0x0378 [7:0] Frequency lock threshold, Bits[23:16] (default: 0x00) 0x0379 [7:0] Frequency lock fill rate Frequency lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle) 0x037A [7:0] Frequency lock drain rate Frequency lock drain rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle) DPLL_0 CONTROLS (REGISTER 0x0400 TO REGISTER 0x0415) Table 73. DPLL_0 Free Run Frequency Tuning Word Address Bits Bit Name Description 0x0400 [7:0] 30-bit free running frequency tuning word Free running frequency tuning word, Bits[7:0]; default: 0x12 0x0401 [7:0] Free running frequency tuning word, Bits[15:8]; default: 0x15 0x0402 [7:0] Free running frequency tuning word, Bits[23:16]; default: 0x64 0x0403 [7:6] Reserved Default: 00b [5:0] 30-bit free running frequency tuning word Free running frequency tuning word, Bits[29:24]; default: 0x1B Table 74. DPLL_0 Digital Oscillator Control Address Bits Bit Name Description 0x0404 [7:5] Reserved Default: 0x0 [4:0] Digital oscillator SDM integer part 0000 to 0011 = invalid 0100 = divide-by-4 0101 = invalid 0110 = divide-by-6 0111 = divide-by-7 1000 = divide-by-8 (default) 1001 = divide-by-9 1010 = divide-by-10 1011 = divide-by-11 1100 = divide-by-12 1101 = divide-by-13 1110 = divide-by-14 1111 = divide-by-15 Table 75. DPLL_0 Frequency Clamp Address Bits Bit Name Description 0x0405 [7:0] Lower limit of pull-in range (expressed as a 20-bit frequency tuning word) Lower limit pull-in range, Bits[7:0] Default: 0x51 0x0406 [7:0] Lower limit pull-in range, Bits[15:8] Default: 0xB8 0x0407 [7:4] Reserved Default: 0x0 [3:0] Lower limit of pull-in range Lower limit pull-in range, Bits[19:16] Default: 0x2 0x0408 [7:0] Upper limit of pull-in range (expressed as a 20-bit frequency tuning word) Upper limit pull-in range, Bits[7:0] Default: 0x3E 0x0409 [7:0] Upper limit pull-in range, Bits[15:8] Default: 0x0A 0x040A [7:4] Reserved Default: 0x0 [3:0] Upper limit of pull-in range Upper limit pull-in range, Bits[19:16] Default: 0xB |
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