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AD9559PCBZ Datasheet(PDF) 19 Page - Analog Devices

Part # AD9559PCBZ
Description  Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
PDF  120 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9559PCBZ Datasheet(HTML) 19 Page - Analog Devices

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Data Sheet
AD9559
Rev. 0 | Page 19 of 120
Pin No.
Mnemonic
Input/
Output
Pin Type
Description
63
XOB
I
Differential
input
Complementary System Clock Input. Complementary signal to XOA. XOB contains
internal dc biasing and should be ac-coupled with a 0.1 μF capacitor except when
using a crystal. When a crystal is used, connect the crystal across XOA and XOB.
64
XOA
I
Differential
input
System Clock Input. XOA contains internal dc biasing and should be ac-coupled
with a 0.01 μF capacitor except when using a crystal. When a crystal is used,
connect the crystal across XOA and XOB. Single-ended 1.8 V CMOS is also an option,
but a spur may be introduced if the duty cycle is not 50%. When using XOA as
a single-ended input, connect a 0.1 μF capacitor from XOB to ground.
70
REFB
I
Differential
input
Reference B Input. This internally biased input is typically ac-coupled; when
configured in this manner, it can accept any differential signal with single-ended
swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.
71
A
REFBE
I
Differential
input
Complementary Reference B Input. Complementary signal to the input provided
on Pin 70.
EP
GND
O
Exposed pad
The exposed pad is the ground connection on the chip. It must be soldered to the
analog ground of the PCB to ensure proper functionality and heat dissipation,
noise, and mechanical strength benefits.



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