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AD9559PCBZ Datasheet(PDF) 64 Page - Analog Devices |
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AD9559PCBZ Datasheet(HTML) 64 Page - Analog Devices |
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64 / 120 page  AD9559 Data Sheet Rev. 0 | Page 64 of 120 Reg Addr (Hex) Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) DPLL_0 Settings for Reference Input C 0x045A Reference priority Reserved REFC priority, Bits[1:0] Enable REFC 0x00 0x045B W2 DPLL_0 loop BW (16 bits) Digital PLL_0 loop BW scaling factor, Bits[7:0] (default: 0x01F4 = 50 Hz) 0xF4 0x045C W2 Digital PLL_0 loop BW scaling factor, Bits[15:8] 0x01 0x045D W2 Reserved Base filter Reserved 0x00 0x045E W2 DPLL_0 N0 divider (17 bits) Digital PLL feedback divider—Integer Part N0, Bits[7:0] 0xCB 0x045F W2 Digital PLL feedback divider—Integer Part N0, Bits[15:8] 0x07 0x0460 W2 Reserved Digital PLL feedback divider— Integer Part N0, Bit 16 0x00 0x0461 DPLL_0 fractional feedback divider (24 bits) Digital PLL fractional feedback divider—FRAC0, Bits[7:0] 0x04 0x0462 Digital PLL fractional feedback divider—FRAC0, Bits[15:8] 0x00 0x0463 Digital PLL fractional feedback divider—FRAC0, Bits[23:16] 0x00 0x0464 W2 DPLL_0 fractional feedback divider modulus (24 bits) Digital PLL feedback divider modulus—MOD0, Bits[7:0] 0x05 0x0465 W2 Digital PLL feedback divider modulus—MOD0, Bits[15:8] 0x00 0x0466 W2 Digital PLL feedback divider modulus—MOD0, Bits[23:16] 0x00 DPLL_0 Settings for Reference Input D 0x0467 Reference priority Reserved REFD priority, Bits[1:0] Enable REFD 0x00 0x0468 W2 DPLL_0 loop BW (16 bits) Digital PLL_0 loop BW scaling factor, Bits[7:0] (default: 0x01F4 = 50 Hz) 0xF4 0x0469 W2 Digital PLL_0 loop BW scaling factor, Bits[15:8] 0x01 0x046A W2 Reserved Base filter Reserved 0x00 0x046B W2 DPLL_0 N0 divider (17 bits) Digital PLL feedback divider—Integer Part N0, Bits[7:0] 0xCB 0x046C W2 Digital PLL feedback divider—Integer Part N0, Bits[15:8] 0x07 0x046D W2 Reserved Digital PLL feedback divider— Integer Part N0, Bit 16 0x00 0x046E DPLL_0 fractional feedback divider (24 bits) Digital PLL fractional feedback divider—FRAC0, Bits[7:0] 0x04 0x046F Digital PLL fractional feedback divider—FRAC0, Bits[15:8] 0x00 0x0470 Digital PLL fractional feedback divider—FRAC0, Bits[23:16] 0x00 0x0471 W2 DPLL_0 fractional feedback divider modulus (24 bits) Digital PLL feedback divider modulus—MOD0, Bits[7:0] 0x05 0x0472 W2 Digital PLL feedback divider modulus—MOD0, Bits[15:8] 0x00 0x0473 W2 Digital PLL feedback divider modulus—MOD0, Bits[23:16] 0x00 DPLL_1 General Settings 0x0500 DPLL_1 free run frequency TW 30-bit free running frequency tuning word, Bits[7:0] 0x12 0x0501 30-bit free running frequency tuning word, Bits[15:8] 0x15 0x0502 30-bit free running frequency tuning word, Bits[23:16] 0x64 0x0503 Reserved 30-bit free running frequency tuning word, Bits[29:24] 0x1B 0x0504 DCO_1 control Reserved Digital oscillator SDM integer part, Bits[3:0] 0x08 0x0505 DPLL_1 frequency clamp Lower limit of pull-in range, Bits[7:0] 0x51 0x0506 Lower limit of pull-in range, Bits[15:8] 0xB8 0x0507 Reserved Lower limit of pull-in range, Bits[19:16] 0x02 0x0508 Upper limit of pull-in range, Bits[7:0] 0x3E 0x0509 Upper limit of pull-in range, Bits[15:8] 0x0A 0x050A Reserved Upper limit of pull-in range, Bits[19:16] 0x0B |
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