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Data Sheet

AD9559

Rev. 0 | Page 89 of 120

DPLL_0 SETTINGS FOR REFERENCE INPUT C (REFC) (REGISTER 0x045A TO REGISTER 0x0466)

Table 98. DPLL_0 REFC Priority Setting

Address

Bits

Bit Name

Description

0x045A

[7:3]

Reserved

Default: 00000b.

[2:1]

REFC priority

These bits set the priority level (0 to 3) of REFC relative to the other input references.

00 (default) = 0 (highest).

01 = 1.

10 = 2.

11 = 3.

Enable REFC

This bit enables DPLL_0 to lock to REFC.

0 (default) = REFC is not enabled for use by DPLL_0.

1 = REFC is enabled for use by DPLL_0.

Table 99. DPLL_0 REFC Loop BW Scaling Factor

Address

Bits

Bit Name

Description

0x045B

[7:0]

DPLL loop BW scaling factor

(unit of 0.1 Hz)

Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4).

0x045C

[7:0]

Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01).

The default for Register 0x045B and Register 0x045C: 0x01F4 = 500 (50 Hz loop BW).

The loop bandwidth should always be less than the DPLL phase detector frequency

divided by 20. The DPLL may not lock reliably if the DPLL loop BW is <50 Hz and a crystal

is used for the system clock. See the Choosing the SYSCLK Source section for details.

0x045D

[7:2]

Reserved

Default: 0x00.

Base loop filter selection

0 = base loop filter with normal (70°) phase margin (default).

1 = base loop filter with high phase margin.

(≤0.1 dB peaking in the closed-loop transfer function for loop BW ≤ 2 kHz. Setting this

bit is also recommended for loop BW > 2 kHz.)

Reserved

Default: 0b.

Table 100. DPLL_0 REFC Integer Part of Feedback Divider

Address

Bits

Bit Name

Description

0x045E

[7:0]

Integer Part N0

DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0xCB).

0x045F

[7:0]

DPLL integer feedback divider, Bits[15:8] (default: 0x07).

0x0460

[7:1]

Reserved

Default: 0x00.

Integer Part N0

DPLL integer feedback divider, Bit 16 (default: 0b).

The default for Register 0x045E to Register 0x460: 0x007CB (which equals N1 = 1996).

Table 101. DPLL_0 REFC Fractional Part of Fractional Feedback Divider FRAC0

Address

Bits

Bit Name

Description

0x0461

[7:0]

Digital PLL fractional

feedback divider—FRAC0

The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04).

0x0462

[7:0]

The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00).

0x0463

[7:0]

The numerator of the fractional-N feedback divider, Bits[23:18] (default: 0x00).

Table 102. DPLL_0 REFC Modulus of Fractional Feedback Divider MOD0

Address

Bits

Bit Name

Description

0x0464

[7:0]

Digital PLL feedback divider

modulus—MOD0

The denominator of the fractional-N feedback divider, Bits[7:0] (default: 0x05).

0x0465

[7:0]

The denominator of the fractional-N feedback divider, Bits[15:8] (default: 0x00).

0x0466

[7:0]

The denominator of the fractional-N feedback divider, Bits[23:17] (default: 0x00).

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