AD9559PCBZ datasheet(28/120 Pages) AD

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AD9559

Data Sheet

Rev. 0 | Page 28 of 120

This section provides a programming overview of the register

blocks in the AD9559, describing what they do and why they

are important. This is supplemental information only, needed

only if the user wishes to load the registers without using the

STP file.

The AD9559 evaluation software contains a wizard that determines

the register settings based on the user’s input and output

frequencies. It is strongly recommended that the evaluation

software be used to determine these settings.

Multifunction Pins (Optional)

This step is required only if the user intends to use any of the

multifunction pins for status or control. The multifunction pin

parameters are at Register 0x0100 to Register 0x0107.

Table 196 has a list of M pin output functions, and Table 197 has

a list of M pin input functions.

IRQ Functions (Optional)

This step is required only if the user intends to use the IRQ feature.

The IRQ functions are divided into three groups: common,

PLL_0, and PLL_1.

The user must first choose the events that trigger an IRQ and

then set them in Register 0x010A to Register 0x0112. Next,

an M pin must be assigned to the IRQ function. The user can

choose to dedicate one M pin to each of the three IRQ groups,

or one M pin can be assigned for all IRQs.

The IRQ monitor registers are located at Register 0x0D08 to

IRQ monitor bit at Register 0x0D08 to Register 0x0D10 is set

high when the indicated event occurs.

Individual IRQ events are cleared by using the IRQ clearing

registers at Register 0x0A05 to Register 0x0A0E or by setting

the clear all IRQs bit (Register 0x0A05[0]) to 1b.

The default values of the IRQ mask registers are such that

interrupts are not generated. The default IRQ pin mode is open-

drain NMOS.

Watchdog Timer (Optional)

This step is required only if the user intends to use the watchdog

timer. The watchdog timer control is at Register 0x0108 and

The watchdog timer is useful for generating an IRQ after a fixed

amount of time. The timer is reset by setting the clear watchdog

timer bit in Register 0x0A05[7] to 1.

The user can also program an M pin for the watchdog timer

output. In this mode, the M pin generates a 40 ns pulse every

time the watchdog timer expires.

System Clock Configuration

The system clock multiplier (SYSCLK) parameters are at

use the following steps:

1. Set the system clock PLL input type and divider values.

2. Set the system clock period.

It is essential to program the system clock period because

many of the AD9559 subsystems rely on this value.

3. Set the system clock stability timer.

It is highly recommended that the system clock stability

timer be programmed. This is especially important when

using the system clock multiplier and also applies when

using an external system clock source, especially if the

external source is not expected to be completely stable

when power is applied to the AD9559. The system clock

stability timer specifies the amount of time that the system

clock PLL must be locked before the part declares that the

system clock is stable. The default value is 50 ms.

4. Update all registers (Register 0x0005 = 0x01).

Important Note

The system clock must be stable for the digital PLL blocks to

function correctly and read back the registers updated on the

system clock domain. These registers include the status registers,

as well as the free running tuning word. Therefore, when debug-

ging the AD9559, the user must first ensure that the system clock is

stable by checking Bit 1 in Register 0x0D01.

Reference Inputs

The reference input parameters and reference dividers are common

to both PLLs; there is only one reference divider (R divider) for

each reference input. The register address for each reference input

is as follows:

•

REFA: Register 0x0300 to Register 0x031A

•

REFB: Register 0x0320 to Register 0x033A

•

REFC: Register 0x0340 to Register 0x035A

•

REFD: Register 0x0360 to Register 0x037A

These registers include the following settings:

•

Reference logic family

•

Reference divider (R divider value)

•

Reference input period and tolerance

•

Reference validation timer

•

Phase and frequency lock detector settings

AD9559PCBZ Datasheet(PDF) 28 Page - Analog Devices

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