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AD9559PCBZ Datasheet(PDF) 68 Page - Analog Devices |
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AD9559PCBZ Datasheet(HTML) 68 Page - Analog Devices |
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68 / 120 page ![]() AD9559 Data Sheet Rev. 0 | Page 68 of 120 Reg Addr (Hex) Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) Common Operational Controls 0x0A00 L Global Reserved Soft sync all Calibrate all Power- down all 0x00 0x0A01 Reference inputs Reserved REFD power- down REFC power- down REFB power- down REFA power- down 0x00 0x0A02 A Reserved REFD timeout REFC timeout REFB timeout REFA timeout 0x00 0x0A03 Reserved REFD fault REFC fault REFB fault REFA fault 0x00 0x0A04 Reserved REFD monitor bypass REFC monitor bypass REFB monitor bypass REFA monitor bypass 0x00 0x0A05 A Clear IRQ groups Clear watchdog timer Reserved Clear DPLL_1 IRQs Clear DPLL_0 IRQs Clear common IRQs Clear all IRQs 0x00 0x0A06 A Clear common IRQ Reserved SYSCLK unlocked SYSCLK stable SYSCLK locked Watchdog timer Reserved EEPROM fault EEPROM complete 0x00 0x0A07 A Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault 0x00 0x0A08 A Reserved REFD validated REFD fault cleared REFD fault Reserved REFC validated REFC fault cleared REFC fault 0x00 0x0A09 A Clear DPLL_0 IRQ Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked 0x00 0x0A0A A DPLL_0 switching DPLL_0 free run DPLL_0 holdover History updated REFD activated REFC activated REFB activated REFA activated 0x00 0x0A0B A Reserved Clock dist sync’d APLL_0 unlocked APLL_0 locked APLL_0 cal ended APLL_0 cal started 0x00 0x0A0C A Clear DPLL_1 IRQ Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked 0x00 0x0A0D A DPLL_1 switching DPLL_1 free run DPLL_1 holdover History updated REFD activated REFC activated REFB activated REFA activated 0x00 0x0A0E A Reserved Clock dist sync’d APLL_1 unlocked APLL_1 locked APLL_1 cal ended APLL_1 cal started 0x00 PLL_0 Operational Controls 0x0A20 PLL_0 sync cal Reserved APLL_0 soft sync APLL_0 calibrate (no self clear) PLL_0 power- down 0x00 0x0A21 PLL_0 output Reserved OUT0B disable OUT0A disable OUT0B power- down OUT0A power- down 0x00 0x0A22 PLL_0 user mode Reserved DPLL_0 manual reference, Bits[1:0] DPLL_0 switching mode, Bits[2:0] DPLL_0 user holdover DPLL_0 user free run 0x00 0x0A23 A PLL_0 reset Reserved Reset DPLL_0 loop filter Reset DPLL_0 TW history Reset DPLL_0 auto sync 0x00 0x0A24 A PLL_0 phase Reserved DPLL_0 reset phase offset DPLL_0 decrement phase offset DPLL_0 increment phase offset 0x00 PLL_1 Operational Controls 0x0A40 PLL_1 sync cal Reserved APLL_1 soft sync APLL_1 calibrate (no self clear) PLL_1 power- down 0x00 0x0A41 PLL_1 output Reserved OUT1B disable OUT1A disable OUT1B power- down OUT1A power- down 0x00 0x0A42 PLL_1 user mode Reserved DPLL_1 manual reference, Bits[1:0] DPLL_1 switching mode, Bits[2:0] DPLL_1 user holdover DPLL_1 user free run 0x00 0x0A43 A PLL_1 reset Reserved Reset DPLL_1 loop filter Reset DPLL_1 TW history Reset DPLL_1 auto sync 0x00 0x0A44 A PLL_1 phase Reserved DPLL_1 reset phase offset DPLL_1 decrement phase offset DPLL_1 increment phase offset 0x00 |
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