AD9559PCBZ datasheet(7/120 Pages) AD

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Data Sheet

AD9559

Rev. 0 | Page 7 of 120

REFERENCE MONITORS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE MONITORS

Reference Monitor

Loss of Reference Detection Time

1.15

DPLL PFD

period

Nominal phase detector period = R/fREF 1

Frequency Out-of Range Limits

105

Δf/fREF

(ppm)

Programmable (lower bound subject to quality

of the system clock (SYSCLK)); SYSCLK accuracy

must be less than the lower bound

Validation Timer

0.001

65.535

sec

Programmable in 1 ms increments

fREF is the frequency of the active reference; R is the frequency division factor determined by the R divider.

REFERENCE SWITCHOVER SPECIFICATIONS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE SWITCHOVER SPECIFICATIONS

Maximum Output Phase Perturbation

(Phase Build-Out Switchover)

Assumes a jitter-free reference; satisfies

Telcordia GR-1244-CORE requirements;

base loop filter selection bit set to 1b for

all active references

50 Hz DPLL Loop Bandwidth

Test conditions: 19.44 MHz to 174.70308 MHz;

DPLL BW = 50 Hz; 49.152 MHz signal generator

used for system clock source

Peak

±55

±100

Steady State

±55

±100

Time Required to Switch to a New Reference

Phase Build-Out Switchover

DPLL PFD

period

Calculated using the nominal phase detector

period (NPDP = R/fREF); the total time required

is the time plus the reference validation time,

plus the time required to lock to the new

reference

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