AD9559PCBZ datasheet(72/120 Pages) AD

72 / 120 page

AD9559

Data Sheet

Rev. 0 | Page 72 of 120

SERIAL CONTROL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005)

Table 35. Serial Configuration (Note that the contents of Register 0x0000 are not stored to the EEPROM.)

Address

Bits

Bit Name

Description

0x0000

SDO enable

Enables SPI port SDO pin.

1 = 4-wire (SDO pin enabled).

0 (default) = 3-wire.

LSB first/increment address

Bit order for SPI port.

1 = least significant bit and byte first.

0 (default) = most significant bit and byte first.

Soft reset

Device reset (invokes an EEPROM download if EEPROM or pin program is enabled.)

See the EEPROM and Pin Configuration and Function Descriptions sections for details.

[4:0]

Reserved

Default: 0x00.

Table 36. Readback Control

Address

Bits

Bit Name

Description

0x0004

[7:5]

Reserved

Default: 0x00.

Reset sans reg map

Resets the part while maintaining the current register settings.

1 = resets the device.

0 (default) = no action.

Disable auto actions

Disables the automatic updating of DPLL parameters.

1 = disables the automatic register write detection functions described in Table 32.

0 (default) = the live registers in the DPLL profile registers update immediately.

Reserved

Default: 0x00.

2-wire SPI

Enables 2-wire SPI mode, in which the

CSE

pin state is ignored. Note that the

CSE

stalled

high function is not available in this mode and that the correct number of clock edges

must be present on the SCLK pin during a transfer.

1 = ignores the state of the

CSE

pin, making the M5/

CSE

pin available as an M pin for

control/status of the AD9559.

0 (default) = normal SPI operation.

Read buffer register

For buffered registers, serial port readback reads from actual (active) registers instead of

the buffer.

1 = reads buffered values that take effect on next assertion of IO_UPDATE.

0 (default) = reads values currently applied to the device’s internal logic.

Table 37. Soft IO_UPDATE

Address

Bits

Bit Name

Description

0x0005

[7:1]

Reserved

Reserved.

IO_UPDATE

Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the device’s

internal control registers. This is an autoclearing bit.

CLOCK PART FAMILY ID (REGISTER 0x000C AND REGISTER 0x000D)

Table 38. Clock Part Family ID

Address

Bits

Bit Name

Description

0x000C

[7:0]

Clock part family ID, Bits[7:0]

The values in this read-only register and Register 0x000D uniquely identify the AD9559.

This is useful in cases where the user’s software must determine which device is located

at a given I²C address.

Default: 0x02 for the AD9559.

0x000D

[7:0]

Clock part family ID, Bits[15:8]

Default: 0x00 for the AD9559.

AD9559PCBZ Datasheet(PDF) 72 Page - Analog Devices

AD9559PCBZ Datasheet(HTML) 72 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL