AD9559PCBZ datasheet(10/120 Pages) AD

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AD9559

Data Sheet

Rev. 0 | Page 10 of 120

TIME DURATION OF DIGITAL FUNCTIONS

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TIME DURATION OF DIGITAL FUNCTIONS

EEPROM-to-Register Download Time

Uses default EEPROM storage sequence (see Register 0x0E10

to Register 0x0E4F)

180

Uses default EEPROM storage sequence (see Register 0x0E10

to Register 0x0E4F

Power-Down Exit Time

Time from power-down exit to system clock lock detect; system

clock stability timer setting should be added to calculate the

time needed for system clock stable

DIGITAL PLL (DPLL_0 AND DPLL_1)

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL PLL

Phase Frequency Detector (PFD) Input

Frequency Range

100

kHz

Loop Bandwidth

0.1

2000

Programmable design parameter;

note that (fPFD/loop BW) ≥ 20

Phase Margin

Degrees

Programmable design parameter

Closed Loop Peaking

<0.1

Programmable design parameter; part can be programmed

for <0.1 dB peaking in accordance with Telcordia GR-253-CORE

jitter transfer

ANALOG PLL (APLL_0 AND APLL_1)

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ANALOG PLL0

VCO Frequency Range

2940

3543

MHz

Phase Frequency Detector (PFD) Input

Frequency Range

180

195

MHz

Loop Bandwidth

240

kHz

Programmable design parameter

Phase Margin

Degrees

Programmable design parameter

ANALOG PLL1

VCO Frequency Range

3405

4260

MHz

Phase Frequency Detector (PFD) Input

Frequency Range

180

195

MHz

Loop Bandwidth

240

kHz

Programmable design parameter

Phase Margin

Degrees

Programmable design parameter

DIGITAL PLL LOCK DETECTION

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PHASE LOCK DETECTOR

Threshold Programming Range

224 − 1

Reference-to-feedback phase difference

Threshold Resolution

FREQUENCY LOCK DETECTOR

Threshold Programming Range

224 − 1

Reference-to-feedback period difference

Threshold Resolution

HOLDOVER SPECIFICATIONS

Table 13.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

HOLDOVER SPECIFICATIONS

Initial Frequency Accuracy

<0.01

ppm

Excludes frequency drift of SYSCLK source; excludes frequency

drift of input reference prior to entering holdover; compliant

with GR-1244 Stratum 3

AD9559PCBZ Datasheet(PDF) 10 Page - Analog Devices

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