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AD9559PCBZ Datasheet(PDF) 71 Page - Analog Devices

Part # AD9559PCBZ
Description  Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
PDF  120 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9559PCBZ Datasheet(HTML) 71 Page - Analog Devices

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Data Sheet
AD9559
Rev. 0 | Page 71 of 120
Reg
Addr
(Hex)
Opt
Name
D7
D6
D5
D4
D3
D2
D1
D0
Def
(Hex)
0x0E2D
DPLL_0
dividers
and BW
Size of transfer: 52 bytes
0x33
0x0E2E
Starting Address 0x0440
0x04
0x0E2F
0x40
0x0E30
DPLL_1
general
settings
Size of transfer: 22 bytes
0x15
0x0E31
Starting Address 0x0500
0x05
0x0E32
0x00
0x0E33
APLL_1
config and
output
drivers
Size of transfer: 15 bytes
0x0E
0x0E34
Starting Address 0x0520
0x05
0x0E35
0x20
0x0E36
DPLL_1
dividers
and BW
Size of transfer: 52 bytes
0x33
0x0E37
Starting Address 0x0540
0x05
0x0E38
0x40
0x0E39
Loop filter
Size of transfer: 24 bytes
0x17
0x0E3A
Starting Address 0x0800
0x08
0x0E3B
0x00
0x0E3C
Common
operational
controls
Size of transfer: 15 bytes
0x0E
0x0E3D
Starting Address 0x0A00
0x0A
0x0E3E
0x00
0x0E3F
PLL_0
operational
controls
Size of transfer: five bytes
0x04
0x0E40
Starting Address 0x0A20
0x0A
0x0E41
0x20
0x0E42
PLL_1
operational
controls
Size of transfer: five bytes
0x04
0x0E43
Starting Address 0x0A40
0x0A
0x0E44
0x40
0x0E45
IO_UPDATE
Command: IO_UPDATE
0x80
0x0E46
Calibrate
APLLs
Command: calibrate output PLLs
0x90
0x0E47
Sync
outputs
Command: distribution sync
0xA0
0x0E48
End of data
Command: end of data
0xFF
0x0E49
to
0x0E4F
Unused
Unused (available for additional data transfers and/or commands)
0x00



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