AD9559PCBZ datasheet(9/120 Pages) AD

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Data Sheet

AD9559

Rev. 0 | Page 9 of 120

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Rise/Fall Time (20% to 80%)1

1.8 V Mode

1.5

10 pF load

3.3 V Strong Mode

0.4

0.6

10 pF load

3.3 V Weak Mode

10 pF load

Duty Cycle

1.8 V Mode

10 pF load

3.3 V Strong Mode

10 pF load

3.3 V Weak Mode

10 pF load

Output Voltage High (VOH)

Output driver static; strong drive strength

VDD3 = 3.3 V, IOH = 10 mA

VDD3 − 0.3

VDD3 = 3.3 V, IOH = 1 mA

VDD3 − 0.1

VDD3 = 1.8 V, IOH = 1 mA

VDD − 0.2

Output Voltage Low (VOL)

Output driver static; strong drive strength

VDD3 = 3.3 V, IOL = 10 mA

0.3

VDD3 = 3.3 V, IOL = 1 mA

0.1

VDD3 = 1.8 V, IOL = 1 mA

0.1

OUTPUT TIMING SKEW

10 pF load

Between OUT0A, OUT0A and OUT0B, OUT0B

or OUT1A, OUT1A and OUT1B, OUT1B

116

265

HSTL mode on both drivers; rising edge only;

any divide value

Additional Delay on One Driver by

Changing Its Logic Type

HSTL to LVDS

+15

+35

Positive value indicates that the LVDS edge is

delayed relative to HSTL

HSTL to 1.8 V CMOS

−5

Positive value indicates that the CMOS edge is

delayed relative to HSTL

OUT0B, OUT0B HSTL to OUT0B, OUT0B

3.3 V CMOS, Strong Mode

−765

−280

+250

The CMOS edge is delayed relative to HSTL

OUT1B, OUT1B HSTL to OUT1B, OUT1B

3.3 V CMOS, Strong Mode

−765

−280

+250

The CMOS edge is delayed relative to HSTL

The listed values are for the slower edge (rising or falling).

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