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AD9559PCBZ Datasheet(PDF) 69 Page - Analog Devices |
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AD9559PCBZ Datasheet(HTML) 69 Page - Analog Devices |
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69 / 120 page  Data Sheet AD9559 Rev. 0 | Page 69 of 120 Reg Addr (Hex) Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) Read-Only Status Common Blocks (These registers are accessible during EEPROM transactions. To show the latest status, Register 0x0D02 to Register 0x0D05 require an IO_UPDATE before being read.) 0x0D00 R, L EEPROM Reserved EEPROM fault detected EEPROM load in progress EEPROM save in progress N/A 0x0D01 R, L SYSCLK and PLL status Reserved PLL_1 all locked PLL_0 all locked SYSCLK stable SYSCLK lock detect N/A 0x0D02 R, L Reference status Reserved DPLL_1 REFA active DPLL_0 REFA active REFA valid REFA fault REFA fast REFA slow N/A 0x0D03 R, L Reserved DPLL_1 REFB active DPLL_0 REFB active REFB valid REFB fault REFB fast REFB slow N/A 0x0D04 R, L Reserved DPLL_1 REFC active DPLL_0 REFC active REFC valid REFC fault REFC fast REFC slow N/A 0x0D05 R, L Reserved DPLL_1 REFD active DPLL_0 REFD active REFD valid REFD fault REFD fast REFD slow N/A 0x0D06 R, L Reserved N/A 0x0D07 R, L Reserved N/A IRQ Monitor 0x0D08 R IRQ, common Reserved SYSCLK unlocked SYSCLK stable SYSCLK locked Watchdog timer Reserved EEPROM fault EEPROM complete N/A 0x0D09 R Reserved REFB validated REFB fault cleared REFB fault Reserved REFA validated REFA fault cleared REFA fault N/A 0x0D0A R Reserved REFD validated REFD fault cleared REFD fault Reserved REFC validated REFC fault cleared REFC fault N/A 0x0D0B R IRQ, DPLL_0 Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked N/A 0x0D0C R DPLL_0 switching DPLL_0 free run DPLL_0 holdover History updated REFD activated REFC activated REFB activated REFA activated N/A 0x0D0D R Reserved Clock dist sync’d APLL_0 unlocked APLL_0 locked APLL_0 cal ended APLL_0 cal started N/A 0x0D0E R IRQ, DPLL_1 Frequency unclamped Frequency clamped Phase slew unlimited Phase slew limited Frequency unlocked Frequency locked Phase unlocked Phase locked N/A 0x0D0F R DPLL_1 switching DPLL_1 free run DPLL_1 holdover History updated REFD activated REFC activated REFB activated REFA activated N/A 0x0D10 R Reserved Clock dist sync’d APLL_1 unlocked APLL_1 locked APLL_1 cal ended APLL_1 cal started N/A PLL_0 Read-Only Status (To show the latest status, these registers require an IO_UPDATE before being read.) 0x0D20 R, L PLL_0 lock status Reserved APLL_0 cal in progress APLL_0 locked DPLL_0 freq lock DPLL_0 phase Lock PLL_0 all locked N/A 0x0D21 R DPLL_0 loop state Reserved DPLL_0 active ref, Bits[1:0] DPLL_0 switching DPLL_0 holdover DPLL_0 free run N/A 0x0D22 R, L Reserved DPLL_0 phase slew limited DPLL_0 frequency clamped DPLL_0 history available N/A 0x0D23 R DPLL_0 holdover history DPLL_0 tuning word readback, Bits[7:0] N/A 0x0D24 R DPLL_0 tuning word readback, Bits[15:8] N/A 0x0D25 R DPLL_0 tuning word readback, Bits[23:16] N/A 0x0D26 R Reserved DPLL_0 tuning word readback, Bits[29:24] N/A 0x0D27 R DPLL_0 phase lock detect bucket DPLL_0 phase lock detect bucket level, Bits[7:0] N/A 0x0D28 R Reserved DPLL_0 phase lock detect bucket level, Bits[11:8] N/A 0x0D29 R DPLL_0 frequency lock detect bucket DPLL_0 frequency lock detect bucket level, Bits[7:0] N/A 0x0D2A R Reserved DPLL_0 frequency lock detect bucket level, Bits[11:8] N/A |
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