AD9559PCBZ datasheet(45/120 Pages) AD

45 / 120 page

Data Sheet

AD9559

Rev. 0 | Page 45 of 120

The controller decodes the number of bytes to transfer directly

from the data instruction itself by adding 1 to the value of the

instruction. For example, Data Instruction 0x1A has a decimal

value of 26; therefore, the controller knows to transfer 27 bytes

(one more than the value of the instruction). When the controller

encounters a data instruction, it knows to read the next two bytes

in the scratchpad because these contain the register map target

address.

Note that, in the EEPROM scratchpad, the two registers that

comprise the address portion of a data instruction have the

MSB of the address in the D7 position of the lower register

address. The bit weight increases left to right, from the lower

starting address always indicates the lowest numbered register

map address in the range of bytes to transfer. That is, the controller

always starts at the register map target address and counts upward,

regardless of whether the serial I/O port is operating in I2C, SPI

LSB-first, or SPI MSB-first mode.

As part of the data transfer process during an EEPROM upload,

the controller calculates a 1-byte checksum and stores it as the

final byte of the data transfer. As part of the data transfer process

during an EEPROM download, however, the controller again

calculates a 1-byte checksum value but compares the newly

calculated checksum with the one that was stored during the

upload process. If an upload/download checksum pair does not

match, the controller sets the EEPROM fault status bit. If the

upload/download checksums match for all data instructions

encountered during a download sequence, the controller sets

the EEPROM complete status bit.

Condition instructions are those that have a value from 0xB0

to 0xBF. The 0xB1 to 0xBF condition instructions represent

Condition 1 to Condition 15, respectively. The 0xB0 condition

instruction is special because it represents the null condition

(see the EEPROM Conditional Processing section).

A pause instruction, like an end instruction, is stored at the end

of a sequence of instructions in the scratchpad. When the con-

troller encounters a pause instruction during an upload sequence,

it keeps the EEPROM address pointer at its last value. Then the

user can store a new instruction sequence in the scratchpad and

upload the new sequence to the EEPROM. The new sequence

is stored in the EEPROM address locations immediately following

the previously saved sequence. This process is repeatable until

an upload sequence contains an end instruction. The pause

instruction is also useful when used in conjunction with condition

processing. It allows the EEPROM to contain multiple occurrences

of the same registers, with each occurrence linked to a set of

conditions (see the EEPROM Conditional Processing section).

EEPROM Upload

To upload data to the EEPROM, the user must first ensure that

the write enable bit (Register 0x0E00, Bit 0) is set. Then, on setting

the autoclearing save to EEPROM bit (Register 0x0E02, Bit 0),

the controller initiates the EEPROM data storage process.

Uploading EEPROM data requires the user to first write an

instruction sequence into the scratchpad registers. During the

upload process, the controller reads the scratchpad data byte-

by-byte, starting at Register 0x0E10 and incrementing the

scratchpad address pointer, as it goes, until it reaches a pause

or end instruction.

As the controller reads the scratchpad data, it transfers the

data from the scratchpad to the EEPROM (byte-by-byte) and

increments the EEPROM address pointer accordingly, unless

it encounters a data instruction. A data instruction tells the

controller to transfer data from the device settings portion of

the register map to the EEPROM. The number of bytes to transfer

is encoded within the data instruction, and the starting address

for the transfer appears in the next two bytes in the scratchpad.

When the controller encounters a data instruction, it stores the

instruction in the EEPROM, increments the EEPROM address

pointer, decodes the number of bytes to be transferred, and

increments the scratchpad address pointer. Then it retrieves

the next two bytes from the scratchpad (the target address)

and increments the scratchpad address pointer by 2. Next, the

controller transfers the specified number of bytes from the register

map (beginning at the target address) to the EEPROM.

When it completes the data transfer, the controller stores

an extra byte in the EEPROM to serve as a checksum for the

transferred block of data. To account for the checksum byte,

the controller increments the EEPROM address pointer by one

more than the number of bytes transferred. Note that, when the

controller transfers data associated with an active register, it actually

transfers the buffered contents of the register (refer to the

Buffered/Active Registers section for details on the difference

between buffered and active registers). This allows for the transfer

of nonzero autoclearing register contents.

Note that conditional processing (see the EEPROM Conditional

Processing section) does not occur during an upload sequence.

Manual EEPROM Download

An EEPROM download results in data transfer from the

EEPROM to the device register map. To download data, the

user sets the autoclearing load from EEPROM bit (Register

0x0E03, Bit 1). This commands the controller to initiate the

EEPROM download process. During download, the controller

reads the EEPROM data byte by byte, incrementing the EEPROM

address pointer as it goes, until it reaches an end instruction.

As the controller reads the EEPROM data, it executes the stored

instructions, which includes transferring stored data to the device

settings portion of the register map whenever it encounters a data

instruction.

Note that conditional processing (see the EEPROM Conditional

Processing section) is applicable only when downloading.

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