AD9559PCBZ datasheet(39/120 Pages) AD

39 / 120 page

Data Sheet

AD9559

Rev. 0 | Page 39 of 120

OUTPUT PLL (APLL)

There are two output PLLs (APLLs) on the AD9559. They

provide the frequency upconversion from the digital PLL

(DPLL) outputs. The frequency range is 2940 MHz to 3543 MHz

for the APLL_0 and 3405 MHz to 4260 MHz for the APLL_1,

while also providing noise filter on the DPLL output. The APLL

reference input is the output of the DPLL. The feedback divider is

an integer divider. The loop filter is partially integrated with the

one external 6.8 nF capacitor that connects to an internal LDO.

The nominal loop bandwidth for both of the APLLs is 240 kHz.

The APLL_0 and APLL_1 block diagrams are shown in Figure 39

and Figure 40, respectively.

LF_0 CAP

LF_0 PIN

VCO_0

3405MHz TO 4260MHz

PFD

FROM DPLL_0

TO P0

DIVIDER

INTEGER DIVIDER

OUTPUT PLL DIVIDER (APLL_0)

÷N0

LDO_0 PIN 10

Figure 39. APLL_0 Block Diagram

VCO_1

3405MHz TO 4260MHz

PFD

FROM DPLL_1

TO P1

DIVIDER

INTEGER DIVIDER

OUTPUT PLL DIVIDER (APLL_1)

÷N1

LF_1 CAP

LF_1 PIN

LDO_1 PIN 45

Figure 40. APLL_1 Block Diagram

APLL CONFIGURATION

The frequency wizard that is included in the evaluation software

configures the APLL, and the user should not need to make

changes to the APLL settings. However, there may be special cases

where the user may wish to adjust the APLL loop bandwidth to

meet a specific phase noise requirement. The easiest way to change

the APLL loop bandwidth is to adjust the APLL charge pump

current in Register 0x0420 (APLL_0) or Register 0x0520 (APLL_1).

There is sufficient stability (68° of phase margin) in the APLL

default settings to permit a broad range of adjustment without

causing the APLL to be unstable. The user should contact

Analog Devices directly if more information is needed.

APLL CALIBRATION

Calibration of the APLLs must be performed at startup and

whenever the nominal input frequency to the APLL changes

by more than ±100 ppm, although the APLL maintains lock

over voltage and temperature extremes without recalibration.

Calibration centers the dc operating voltage at the input to the

APLL VCO.

APLL calibration at startup is normally performed during initial

this datasheet.

To recalibrate the APLL VCO after the chip has been running,

first input the new settings (if any). Ensure that the system clock

is still locked and stable, and that the DPLL is in free run mode

with the free run tuning word set to the same output frequency

that is used when the DPLL is locked. The user can calibrate

APLL_0 without disturbing APLL_1 and vice versa.

Use the following steps to recalibrate the APLL VCO.

Important: An IO_UPDATE (Register 0x0005 = 0x01)

is needed after each of these steps.

1. Ensure that the system clock is locked and stable.

(Register 0x0D01[1] = 1b).

2. Ensure that the DPLL free run tuning word is set.

DPLL_0: Register 0x0400 to Register 0x0403

DPLL_1: Register 0x0500 to Register 0x0503

3. Set free run mode for the appropriate DPLL.

DPLL_0: Register 0x0A22[0] = 1b

DPLL_1: Register 0x0A42[0] = 1b

4. Clear APLL calibration bit.

APLL_0: Register 0x0A20 = 0x00

APLL_1: Register 0x0A40 = 0x00

5. Set APLL calibration bit.

APLL_0: Register 0x0A20 = 0x02

APLL_1: Register 0x0A40 = 0x02

6. Poll the APLL lock status.

APLL_0: Register 0x0D20[3] = 1b indicates lock.

APLL_1: Register 0x0D40[3] = 1b indicates lock.

7. Clear the DPLL mode for the appropriate DPLL.

DPLL_0: Register 0x0A22[0] = 0b

DPLL_1: Register 0x0A42[0] = 0b

AD9559PCBZ Datasheet(PDF) 39 Page - Analog Devices

AD9559PCBZ Datasheet(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL