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AD9559PCBZ Datasheet(PDF) 65 Page - Analog Devices |
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AD9559PCBZ Datasheet(HTML) 65 Page - Analog Devices |
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65 / 120 page  Data Sheet AD9559 Rev. 0 | Page 65 of 120 Reg Addr (Hex) Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def (Hex) 0x050B DPLL_1 holdover history History accumulation timer (ms), Bits[7:0] (up to 65 sec) 0x0A 0x050C History accumulation timer (ms), Bits[15:8] (up to 65 sec] 0x00 0x050D DPLL_1 history mode Reserved Single sample fallback Persistent history Incremental average 0x00 0x050E DPLL_1 closed loop phase offset [±0.5 ms] Fixed phase offset (signed; ps), Bits[7:0] 0x00 0x050F Fixed phase offset (signed; ps), Bits[15:8] 0x00 0x0510 Fixed phase offset (signed; ps), Bits[23:16] 0x00 0x0511 Reserved Fixed phase offset (signed; ps), Bits[29:24] 0x00 0x0512 Incremental phase offset step size (ps/step), Bits[7:0] (up to 65.5 ns/step) 0x00 0x0513 Incremental phase offset step size (ps/step), Bits[15:8] (up to 65.5 ns/step) 0x00 0x0514 DPLL_1 phase slew limit Phase slew rate limit (µs/sec), Bits[7:0] (315 µs/sec up to 65.536 ms/sec) 0x00 0x0515 Phase slew rate Limit (µs/sec), Bits[15:8] (315 µs/sec up to 65.536 ms/sec) 0x00 Output PLL_1 (APLL_1) and Channel 1 Output Drivers 0x0520 APLL _1 charge pump Output PLL1 (APLL_1) charge pump current, Bits[7:0] 0x81 0x0521 APLL_1 M1 divider Output PLL0 (APLL_1) feedback (M1) divider, Bits[7:0] 0x14 0x0522 APLL_1 loop filter control APLL_1 loop filter control, Bits[7:0] 0x07 0x0523 Reserved Bypass internal Rzero 0x00 0x0524 P1 divider Reserved P1 divider divide ratio, Bits[3:0] 0x04 0x0525 OUT1 sync Reserved Sync source selection Auto sync mode 0x00 0x0526 Reserved APLL_1 locked controlled sync disable Mask OUT1B sync Mask OUT1A sync 0x00 0x0527 OUT1A Reserved OUT1A format, Bits[2:0] OUT1A polarity, Bits[1:0] OUT1A LVDS boost Reserved 0x10 0x0528 Q1_A divider, Bits[7:0] 0x00 0x0529 Reserved Q1_A divider, Bits[9:8] 0x00 0x052A Reserved Q1_A divider phase, Bits[5:0] 0x00 0x052B OUT1B Enable 3.3 V CMOS driver OUT1B format, Bits[2:0] OUT1B polarity, Bits[1:0] OUT1B LVDS boost Reserved 0x10 0x052C Q1_B divider, Bits[7:0] 0x03 0x052D Reserved Q1_B divider, Bits[9:8] 0x00 0x052E Reserved Q1_B divider phase, Bits[5:0] 0x00 DPLL_1 Settings for Reference Input C 0x0540 Reference priority Reserved REFC priority, Bits[1:0] Enable REFC 0x01 0x0541 W2 DPLL_1 loop BW (16 bits) Digital PLL_1 loop BW scaling factor, Bits[7:0] (default: 0x01F4 = 50 Hz) 0xF4 0x0542 W2 Digital PLL_1 loop BW scaling factor, Bits[15:8] 0x01 0x0543 W2 Reserved Base filter Reserved 0x00 0x0544 W2 DPLL_1 N1 divider (17 bits) Digital PLL_1 feedback divider—Integer Part N1, Bits[7:0] 0xCB 0x0545 W2 Digital PLL_1 feedback divider—Integer Part N1, Bits[15:8] 0x07 0x0546 W2 Reserved Digital PLL feedback divider— Integer Part N1, Bit 16 0x00 0x0547 DPLL_1 fractional feedback divider (24 bits) Digital PLL_1 fractional feedback divider—FRAC1, Bits[7:0] 0x04 0x0548 Digital PLL_1 fractional feedback divider—FRAC1, Bits[15:8] 0x00 0x0549 Digital PLL_1 fractional feedback divider—FRAC1, Bits[23:16] 0x00 |
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