AD9559PCBZ datasheet(56/120 Pages) AD

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AD9559

Data Sheet

Rev. 0 | Page 56 of 120

PROGRAMMING THE I/O REGISTERS

The register map (see Table 34) spans an address range from

0x0000 through 0x0E4F. Each address provides access to one

byte (eight bits) of data. Each individual register is identified by

its four-digit hexadecimal address (for example, Register 0x0A23).

In some cases, a group of addresses collectively defines a register.

In general, when a group of registers defines a control parameter,

the LSB of the value resides in the D0 position of the register

with the lowest address. The bit weight increases right to left,

from the lowest register address to the highest register address.

Note that the EEPROM storage sequence registers (Address 0x0E10

to Address 0x0E4F) are an exception to this convention (see the

EEPROM Instructions section).

BUFFERED/ACTIVE REGISTERS

There are two copies of most registers: buffered and active. The

value in the active registers is the one that is in use. The buffered

registers are the ones that take effect the next time the user writes

0x01 to Register 0x0005 (IO_UPDATE). Buffering the registers

allows the user to update a group of registers (like the APLL

settings) simultaneously, avoiding the potential of unpredictable

behavior in the part. Registers with an L in the option column of

the register map (see Table 34) are live, meaning that they take

effect the moment the serial port transfers that data byte.

WRITE DETECT REGISTERS

A W in the option column of the register map (see Table 34)

identifies a register with write detection. These registers contain

additional logic to avoid glitches or unwanted operation. Write

detection can be disabled by setting Register 0x0004, Bit 3 to 1b.

Table 32. Register Write Detection Description

Option

The input reference is immediately faulted when

these registers are written to, and the input

reference validation timer restarts when the next

IO_UPDATE occurs (Register 0x0005 = 0x01).

The lock detector declares unlock immediately

when these registers are written to, and the lock

detection restarts when the next IO_UPDATE occurs.

After these registers are written to, the DPLL

automatically enters holdover for one PFD cycle

(and then exits) when an IO_UPDATE is issued.

The watchdog timer resets automatically when

these registers are changed, and then resumes

counting on the next IO_UPDATE.

The system clock stability timer is automatically

reset when these registers are changed, and

then resumes counting on the next IO_UPDATE.

If these registers are written to while they are

assigned to an existing function, the existing function

stops immediately. The new function starts when

the next IO_UPDATE occurs.

AUTOCLEAR REGISTERS

An A in the option column of the register map (see Table 34)

identifies an autoclearing register. Typically, the active value for

an auto-clearing register takes effect following an IO_UPDATE.

The bit is cleared by the internal device logic upon completion

of the prescribed action.

Read and write access to the register map may be restricted,

depending on the register in question, the source and direction

of access, and the current state of the device. Each register can

be classified into one or more access types. When more than

one type applies, the most restrictive condition is the one that

applies.

When access is denied to a register, all attempts to read the register

return a 0 byte, and all attempts to write to the register are ignored.

Access to nonexistent registers is handled in the same way as for

a denied register.

Regular Access

Registers with regular access do not fall into any other category.

Both read and write access to registers of this type can be from

either the serial ports or EEPROM controller. However, only

one of these sources can have access to a register at any given

time (access is mutually exclusive). When the EEPROM controller

is active, either in load or store mode, it has exclusive access to

these registers.

Read-Only Access

An R in the option column of the register map (see Table 34)

identifies read-only registers. Access is available at all times,

including when the EEPROM controller is active. Note that

read-only registers (R) are inaccessible to the EEPROM as well.

Exclusion from EEPROM Access

An E in the option column of the register map (see Table 34)

identifies a register with contents that are inaccessible to the

EEPROM. That is, the contents of this type of register cannot be

transferred directly to the EEPROM or vice versa. Note that

read-only registers (R) are inaccessible to the EEPROM as well.

AD9559PCBZ Datasheet(PDF) 56 Page - Analog Devices

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