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AD9559

Data Sheet

Rev. 0 | Page 90 of 120

DPLL_0 SETTINGS FOR REFERENCE INPUT D (REFD) (REGISTER 0x0467 TO REGISTER 0x0473)

Table 103. DPLL_0 REFD Priority Setting

Address

Bits

Bit Name

Description

0x0467

[7:3]

Reserved

Default: 00000b.

[2:1]

REFD priority

These bits set the priority level (0 to 3) of REFD relative to the other input references.

00 (default) = 0 (highest).

01 = 1.

10 = 2.

11 = 3.

Enable REFD

This bit enables DPLL_0 to lock to REFD.

0 (default) = REFD is not enabled for use by DPLL_0.

1 = REFD is enabled for use by DPLL_0.

Table 104. DPLL_0 REFD Loop BW Scaling Factor

Address

Bits

Bit Name

Description

0x0468

[7:0]

DPLL loop BW scaling factor

(unit of 0.1 Hz)

Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4).

0x0469

[7:0]

Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01).

The default for Register 0x0468 and Register 0x0469 = 0x01F4 = 500 (50 Hz loop BW).

The loop bandwidth should always be less than the DPLL phase detector frequency

divided by 20. The DPLL may not lock reliably if the DPLL loop BW is <50 Hz and a crystal

is used for the system clock. See the Choosing the SYSCLK Source section for details.

0x046A

[7:2]

Reserved

Default: 0x00.

Base loop filter selection

0 = base loop filter with normal (70°) phase margin (default).

1 = base loop filter with high phase margin.

(≤0.1 dB peaking in the closed-loop transfer function for loop BWs ≤ 2 kHz. Setting this

bit is also recommended for loop BW > 2 kHz.)

Reserved

Default: 0b.

Table 105. DPLL_0 REFD Integer Part of Feedback Divider

Address

Bits

Bit Name

Description

0x046B

[7:0]

Integer Part N0

DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0xCB).

0x046C

[7:0]

DPLL integer feedback divider, Bits[15:8] (default: 0x07).

0x046D

[7:1]

Reserved

Default: 0x00.

Integer Part N0

DPLL integer feedback divider, Bit 17 (default: 0b).

The default for Register 0x046B to Register 0x46D: 0x007CB (which equals N1 = 1996).

Table 106. DPLL_0 REFD Fractional Part of Fractional Feedback Divider FRAC0

Address

Bits

Bit Name

Description

0x046E

[7:0]

Digital PLL fractional

feedback divider—FRAC0

The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04)

0x046F

[7:0]

The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)

0x0470

[7:0]

The numerator of the fractional-N feedback divider, Bits[23:18] (default: 0x00)

Table 107. DPLL_0 REFD Modulus of Fractional Feedback Divider MOD0

Address

Bits

Bit Name

Description

0x0471

[7:0]

Digital PLL feedback divider

modulus—MOD0

The denominator of the fractional-N feedback divider, Bits[7:0] (default: 0x05)

0x0472

[7:0]

The denominator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)

0x0473

[7:0]

The denominator of the fractional-N feedback divider, Bits[23:17] (default: 0x00)

AD9559PCBZ Datasheet(PDF) 90 Page - Analog Devices

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