AD9559PCBZ datasheet(38/120 Pages) AD

Part #	AD9559PCBZ

Description	Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

PDF	120 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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38 / 120 page

AD9559

Data Sheet

Rev. 0 | Page 38 of 120

System Clock Stability Timer

Because the reference monitors depend on the system clock

being at a known frequency, it is important that the system clock

be stable before activating the monitors. At initial power-up,

the system clock status is not known; therefore, it is reported as

being unstable. After the part has been programmed, the system

clock PLL eventually locks.

When a stable operating condition is detected, a timer is run

for the duration that is stored in the system clock stability

period registers. If, at any time during this waiting period, the

condition is violated, the timer is reset and halted until a stable

condition is reestablished. After the specified period elapses,

the AD9559 reports the system clock as stable.

Note that, any time the system clock stability timer is changed in

The system clock stability timer starts counting when the next

IO_UDATE is issued.

AD9559PCBZ Datasheet(PDF) 38 Page - Analog Devices