AD6684 datasheet(40/107 Pages) AD

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AD6684

Data Sheet

Rev. 0 | Page 40 of 107

For example, if the ADC sampling frequency (fS) is 500 MSPS

and the carrier frequency (fC) is 140.312 MHz, then

NCO_FTW = round

















500

312

140

mod

7.89886 × 1013 Hz

This, in turn, converts to 0x47D in the 48-bit twos complement

representation for NCO_FTW. The actual carrier frequency,

fC_ACTUAL, is calculated based on the following equation:

fC_ACTUAL =

FTW

NCO



= 140.312 MHz

A 48-bit POW is available for each NCO to create a known phase

relationship between multiple AD6684 chips or individual DDC

channels inside one AD6684 chip.

The POW registers can be updated in the NCO at any time

without disrupting the phase accumulators, allowing phase

adjustments to occur during normal operation. However, the

following procedure must be followed to update the FTW

registers to ensure proper operation of the NCO:

Write to the FTW registers for all the DDCs.

Synchronize the NCOs either through the DDC NCO soft

reset bit (Register 0x0300, Bit 4), which is accessible

through the SPI, or through the assertion of the SYSREF±

pin.

It is important to note that the NCOs must be synchronized

either through the SPI or through the SYSREF± pin after all

writes to the FTW or POW registers are complete. This step

is necessary to ensure the proper operation of the NCO.

NCO Synchronization

Each NCO contains a separate phase accumulator word (PAW).

The initial reset value of each PAW is set to zero, and the phase

increment value of each PAW is determined by the FTW. The

POW is added to the PAW to produce the instantaneous phase

of the NCO. See the Setting Up the NCO FTW and POW section

for more information.

Use the following two methods to synchronize multiple PAWs

within the chip.



Using the SPI. Use the DDC NCO soft reset bit in the DDC

synchronization control register (Register 0x0300, Bit 4) to

reset all the PAWs in the chip. This is accomplished by

setting the DDC NCO soft reset bit high and then setting

this bit low. Note that this method can only be used to

synchronize DDC channels within the same pair (A/B or

C/D) of a AD6684 chip.



Using the SYSREF± pin. When the SYSREF± pin is enabled

in the SYSREF± control registers (Register 0x0120 and

in the DDC synchronization control register (Register 0x0300,

Bits[1:0]), any subsequent SYSREF± event resets all the

PAWs in the chip. Note that this method can be used to

synchronize DDC channels within the same AD6684 chip

or DDC channels within separate AD6684 chips.

Mixer

The NCO is accompanied by a mixer. Its operation is similar to

an analog quadrature mixer. It performs the downconversion of

input signals (real or complex) by using the NCO frequency as a

local oscillator. For real input signals, this mixer performs a real

mixer operation (with two multipliers). For complex input

signals, the mixer performs a complex mixer operation (with

four multipliers and two adders). The mixer adjusts its operation

based on the input signal (real or complex) provided to each

individual channel. The selection of real or complex inputs can

be controlled individually for each DDC block using Bit 7 of the

DDC control registers (Register 0x0310 and Register 0x0330) in

conjunction with the pair index register (Register 0x0009).

AD6684 Datasheet(PDF) 40 Page - Analog Devices

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