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AD6684 Datasheet(PDF) 33 Page - Analog Devices

Part # AD6684
Description  135 MHz Quad IF Receiver
PDF  107 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6684 Datasheet(HTML) 33 Page - Analog Devices

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Data Sheet
AD6684
Rev. 0 | Page 33 of 107
NCO
+
MIXER
(OPTIONAL)
DDC 1
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 2
Q CONVERTER 3
I
Q
NCO
+
MIXER
(OPTIONAL)
DDC 0
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 0
Q CONVERTER 1
I
Q
NCO
+
MIXER
(OPTIONAL)
DDC 1
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 2
Q CONVERTER 3
I
Q
NCO
+
MIXER
(OPTIONAL)
DDC 0
SYSREF±
REAL/I
REAL/Q
REAL/I
CONVERTER 0
Q CONVERTER 1
I
Q
ADC
SAMPLING
AT
fS
REAL/I
ADC
SAMPLING
AT
fS
REAL/Q
ADC
SAMPLING
AT
fS
REAL/I
ADC
SAMPLING
AT
fS
REAL/Q
SYNCHRONIZATION
CONTROL CIRCUITS
SYSREF
L
JESD204B
LANES
AT UP TO
15Gbps
L
JESD204B
LANES
AT UP TO
15Gbps
Figure 73. DDC Detailed Block Diagram
Figure 74 shows an example usage of one of the four DDC
blocks with a real input signal and four half-band filters (HB4 +
HB3 + HB2 + HB1). It shows both complex (decimate by 16)
and real (decimate by 8) output options.
When DDCs have different decimation ratios, the chip
decimation ratio (Register 0x0201) must be set to the lowest
decimation ratio of all the DDC blocks on a per pair basis in
conjunction with the pair index (Register 0x0009). In this
scenario, samples of higher decimation ratio DDCs are repeated
to match the chip decimation ratio sample rate. Whenever the
NCO frequency is set or changed, the DDC soft reset must be
issued. If the DDC soft reset is not issued, the output may
potentially show amplitude variations.
Table 10, Table 11, Table 12, Table 13, and Table 14 show the
DDC samples when the chip decimation ratio is set to 1, 2, 4, 8,
or 16, respectively. When DDCs have different decimation
ratios, the chip decimation ratio must be set to the lowest
decimation ratio of all the DDC channels in the respective
channel pair (Channel A/Channel B or Channel C/Channel D).
In this scenario, samples of higher decimation ratio DDCs are
repeated to match the chip decimation ratio sample rate.



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