AD6684 datasheet(23/107 Pages) AD

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Data Sheet

AD6684

Rev. 0 | Page 23 of 107

THEORY OF OPERATION

ADC ARCHITECTURE

The architecture of the AD6684 consists of an input buffered

pipelined ADC. The input buffer is designed to provide a 200 Ω

termination impedance to the analog input signal. The equivalent

circuit diagram of the analog input termination is shown in

Figure 45.

The input buffer provides a linear high input impedance (for

ease of drive) and reduces kickback from the ADC. The buffer

is optimized for high linearity, low noise, and low power. The

quantized outputs from each stage are combined into a final

14-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate with a new input

sample while, at the same time, the remaining stages operate

with the preceding samples. Sampling occurs on the rising edge

of the clock.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD6684 is a differential buffer with an

internal common-mode voltage of 1.34 V. The clock signal

alternately switches the input circuit between sample mode and

hold mode. Either a differential capacitor or two single-ended

capacitors can be placed on the inputs to provide a matching

passive network. This configuration ultimately creates a low-pass

filter at the input, which limits unwanted broadband noise. See

Figure 57 and Figure 58 for details on input network recom-

mendations. For more information, see the Analog Dialogue

article “Transformer-Coupled Front-End for Wideband A/D

Converters” (Volume 39, April 2005). In general, the precise

values depend on the application.

For best dynamic performance, the source impedances driving

VIN+x and VIN−x must be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference

buffer creates a differential reference that defines the span of the

ADC core.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD6684, the available span is programmable through the SPI

port from 1.44 V p-p to 2.16 V p-p differential with 1.80 V p-p

differential being the default.

Dither

The AD6684 has internal on-chip dither circuitry that improves

the ADC linearity and SFDR, particularly at smaller signal levels. A

known but random amount of white noise is injected into the

input of the AD6684. This dither improves the small signal linearity

within the ADC transfer function and is precisely subtracted

out digitally. The dither is turned on by default and does not

reduce the ADC input dynamic range. The data sheet specifications

and limits are obtained with the dither turned on. The dither

can be disabled using SPI writes to Register 0x0922. Disabling

the dither can slightly improve the SNR (by about 0.2 dB) at the

expense of the small signal SFDR.

Differential Input Configurations

There are several ways to drive the AD6684, either actively or

passively. However, optimum performance is achieved by

driving the analog input differentially.

For applications where SNR and SFDR are key parameters,

differential transformer coupling is the recommended input

configuration (see Figure 57 and Figure 58) because the noise

performance of most amplifiers is not adequate to achieve the

true performance of the AD6684.

For low to midrange frequencies, a double balun or double

transformer network (see Figure 57) is recommended for

optimum performance of the AD6684. For higher frequencies

in the second or third Nyquist zones, it is recommended to

remove some of the front-end passive components to ensure

wideband operation (see Figure 58).

Input Common Mode

The analog inputs of the AD6684 are internally biased to the

common mode as shown in Figure 56.

For dc-coupled applications, the recommended operation

procedure is to export the common-mode voltage to the

VCM_CD/VREF pin using the SPI writes listed in this section.

The common-mode voltage must be set by the exported value

to ensure proper ADC operation. Disconnect the internal

common-mode buffer from the analog input using

When performing SPI writes for dc coupling operation, use the

following register settings in order:

Set Register 0x1908, Bit 2 to 1; this setting disconnects the

internal common-mode buffer from the analog input.

Set Register 0x18A6 to 0x00; this setting turns off the

voltage reference.

Set Register 0x18E6 to 0x00; this setting turns off the

temperature diode export.

Set Register 0x18E0 to 0x04.

Set Register 0x18E1 to 0x1C.

Set Register 0x18E2 to 0x14.

Set Register 0x18E3, Bit 6 to 0x01; this setting turns on the

VCM export.

Set Register 0x18E3, Bits[5:0] to the buffer current setting

(copy the buffer current setting from Register 0x1A4C and

mode export).

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