AD6684 datasheet(67/107 Pages) AD

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Data Sheet

AD6684

Rev. 0 | Page 67 of 107

SYSREF± SETUP/HOLD WINDOW MONITOR

To ensure a valid SYSREF signal capture, the AD6684 has a

SYSREF± setup/hold window monitor. This feature allows the

system designer to determine the location of the SYSREF± signals

relative to the CLK± signals by reading back the amount of

setup/hold margin on the interface through the memory map.

Figure 102 and Figure 103 show the setup and hold status values

for different phases of SYSREF±. The setup detector returns the

status of the SYSREF± signal before the CLK± edge, and the

hold detector returns the status of the SYSREF± signal after the

CLK± edge. Register 0x0128 stores the status of SYSREF± and

lets the user know if the SYSREF± signal is captured by the ADC.

VALID

REG 0x0128[3:0]

CLK±

INPUT

SYSREF±

INPUT

FLIP FLOP

HOLD (MIN)

FLIP FLOP

HOLD (MIN)

FLIP FLOP

SETUP (MIN)

0xF

0xE

0xD

0xC

0xB

0xA

0x9

0x8

0x7

0x6

0x5

0x4

0x3

0x2

0x1

0x0

Figure 102. SYSREF± Setup Detector

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