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AD6684 Datasheet(PDF) 64 Page - Analog Devices |
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AD6684 Datasheet(HTML) 64 Page - Analog Devices |
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64 / 107 page  AD6684 Data Sheet Rev. 0 | Page 64 of 107 LATENCY END-TO-END TOTAL LATENCY Total latency in the AD6684 is dependent on the various digital signal processing (DSP) and JESD204B configuration modes. Latency is fixed at 28 encode clocks through the ADC itself, but the latency through the DSP and JESD204B blocks can vary greatly, depending on the configuration. Therefore, the total latency must be calculated based on the DSP options selected and the JESD204B configuration. Table 36 shows the combined latency through the ADC, DSP, and JESD204B blocks for some of the different application modes supported by the AD6684. Latency is in units of the encode clock. Table 36. Latency Through the AD6684 ADC Application Mode JESD204B Transport Layer Settings Latency (Number of Encode Clocks) L M F ADC + DSP JESD204B Total Full Bandwidth (9-Bit) 2 2 2 30 14 44 DDC (HB1)1 2 4 4 92 17 109 DDC (HB2 + HB1)1 1 4 8 162 13 175 DDC (HB3 +HB2 + HB1)1 1 4 8 292 28 320 DDC (HB4 + HB3 + HB2 + HB1)1 1 4 8 548 39 587 Decimate by 2 + NSR 1 2 4 64 6 70 NSR 2 2 2 38 16 54 1 No mixer, complex outputs. |
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