AD6684 datasheet(26/107 Pages) AD

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AD6684

Data Sheet

Rev. 0 | Page 26 of 107

CLOCK INPUT CONSIDERATIONS

For optimum performance, drive the AD6684 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled to the CLK+ and CLK− pins via a

transformer or clock drivers. These pins are biased internally

and require no additional biasing.

Figure 62 shows a preferred method for clocking the AD6684. The

low jitter clock source is converted from a single-ended signal to

a differential signal using an RF transformer.

ADC

CLK+

CLK–

0.1µF

100Ω

50Ω

CLOCK

INPUT

1:1Z

Figure 62. Transformer-Coupled Differential Clock

Another option is to ac couple a differential CML or LVDS

signal to the sample clock input pins, as shown in Figure 63 and

Figure 64.

ADC

CLK+

CLK–

0.1µF

Z0 = 50Ω

33Ω

71Ω

10pF

3.3V

Figure 63. Differential CML Sample Clock

ADC

CLK+

CLK–

0.1µF

50Ω1

100Ω

CLOCK INPUT

LVDS

DRIVER

CLK+

CLK–

150Ω RESISTORS ARE OPTIONAL.

CLOCK INPUT

Figure 64. Differential LVDS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. The AD6684 contains an

internal clock divider and a duty cycle stabilizer (DCS). In

applications where the clock duty cycle cannot be guaranteed to

be 50%, a higher multiple frequency clock along with the usage

of the clock divider is recommended. When it is not possible to

provide a higher frequency clock, it is recommended to turn on

the DCS using Register 0x011C. The output of the divider offers

a 50% duty cycle, high slew rate (fast edge) clock signal to the

internal ADC. See the Memory Map section for more details on

using this feature.

Input Clock Divider

The AD6684 contains an input clock divider with the ability to

divide the input clock by 1, 2, 4, and 8. The divider ratios can be

selected using Register 0x0108 (see Figure 65).

In applications where the clock input is a multiple of the sample

clock, care must be taken to program the appropriate divider

ratio into the clock divider before applying the clock signal.

This ratio ensures that the current transients during device

startup are controlled.

CLK+

CLK–

÷2

÷4

REG 0x0108

÷8

Figure 65. Clock Divider Circuit

The AD6684 clock divider can be synchronized using the external

SYSREF± input. A valid SYSREF± causes the clock divider to

reset to a programmable state. This synchronization feature

allows multiple devices to have their clock dividers aligned to

guarantee simultaneous input sampling.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input

frequency (fA) due only to aperture jitter (tJ) can be calculated by

SNR = −20 × log (2 × π × fA × tJ)

In this equation, the rms aperture jitter represents the root

mean square of all jitter sources, including the clock input,

analog input signal, and ADC aperture jitter specifications. IF

undersampling applications are particularly sensitive to jitter

(see Figure 66).

130

120

110

100

1000

10000

ANALOG INPUT FREQUENCY (MHz)

12.5

100

200

400

800

Figure 66. Ideal SNR vs. Analog Input Frequency and Jitter

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