AD6684 datasheet(48/107 Pages) AD

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AD6684

Data Sheet

Rev. 0 | Page 48 of 107

Chip

Application

Layer

Chip

Decimation

Ratio

DDC Input

Type

DDC

Output

Type

Bandwidth

Per DDC1

No. of

Virtual

Converters

Required

Two DDCs

Real

5% × fS

0x0009 = 0x01, 0x02, or 0x03 (pair selection)

0x0200 = 0x22 (two DDCs; I only selected)

0x0201 = 0x03 (chip decimate by 8)

0x0310, 0x0330 = 0x4A (real mixer; 6 dB gain;

variable IF; real output; HB4 + HB3 + HB2 + HB1

filters)

0x0311 = 0x00 (DDC 0 I input = ADC Channel A/

Channel C; DDC 0 Q input = ADC Channel A/

Channel C)

0x0331 = 0x05 (DDC 1 I input = ADC Channel B/

Channel D; DDC 1 Q input = ADC Channel B/

Channel D)

0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =

FTW and POW set as required by application for

DDC 0

0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342=

FTW and POW set as required by application for

DDC 1

1 fS is the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection.

2 The NCOs must be synchronized either through the SPI or through the SYSREF± pin after all writes to the FTW or POW registers have completed. This is necessary to

ensure the proper operation of the NCO. See the NCO Synchronization section for more information.

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