AD6684 datasheet(65/107 Pages) AD

65 / 107 page

Data Sheet

AD6684

Rev. 0 | Page 65 of 107

MULTICHIP SYNCHRONIZATION

The AD6684 has a SYSREF± input that provides flexible options

for synchronizing the internal blocks. The SYSREF± input is a

source synchronous system reference signal that enables multichip

synchronization. The input clock divider, DDCs, signal monitor

block, and JESD204B link can be synchronized using the SYSREF±

input. For the highest level of timing accuracy, SYSREF± must

meet setup and hold requirements relative to the CLK± input.

The flowchart in Figure 101 describes the internal mechanism

for multichip synchronization in the AD6684. The AD6684

supports several features that aid users in meeting the requirements

set out for capturing a SYSREF± signal. The SYSREF sample

event can be defined as either a synchronous low to high transition,

or a synchronous high to low transition. Additionally, the AD6684

allows the SYSREF± signal to be sampled using either the rising

edge or falling edge of the CLK± input. The AD6684 also has the

ability to ignore a programmable number (up to 16) of SYSREF±

events. The SYSREF± control options can be selected using

AD6684 Datasheet(PDF) 65 Page - Analog Devices