AD6684 datasheet(62/107 Pages) AD

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AD6684

Data Sheet

Rev. 0 | Page 62 of 107

Example 1: ADC with DDC Option (Two ADCs Plus Two

DDCs in Each Pair)

The chip application mode is DDC mode (seeFigure 99) with

the following characteristics:



Chip application mode = two DDC mode (see Figure 99)



Two 14-bit converters at 500 MSPS



Two DDC application layer mode with complex outputs (I/Q)



Chip decimation ratio = 4



DDC decimation ratio = 4 (see Table 33)

The JESD204B output configuration is as follows:



Virtual converters required = 4 (see Table 33)



Output sample rate (fOUT) = 500/4 = 125 MSPS



N΄ = 16 bits



N = 16 bits



L = 1, M = 4, and F = 8 (quick configuration = 0x13)



CS = 0 to 1



K = 32



Output serial line rate = 5 Gbps per lane (L = 1) or

2.5 Gbps per lane (L = 2)

For L = 1, set Bits[7:4] to 0x1 in Register 0x056E. For L = 2, set

Bits[7:4] to 0x5 in Register 0x056E.

Example 1 shows the flexibility in the digital and lane

configurations for the AD6684. The sample rate is 500 MSPS,

but the outputs are all combined in either one or two lanes,

depending on the I/O speed capability of the receiving device.

NCO

MIXER

(OPTIONAL)

DDC 1

SYSREF±

REAL/I

REAL/Q

REAL/I

CONVERTER 2

Q CONVERTER 3

NCO

MIXER

(OPTIONAL)

DDC 0

SYSREF±

REAL/I

REAL/Q

REAL/I

CONVERTER 0

Q CONVERTER 1

JESD204B

LANES

AT UP TO

15Gbps

NCO

MIXER

(OPTIONAL)

DDC 1

SYSREF±

REAL/I

REAL/Q

REAL/I

CONVERTER 2

Q CONVERTER 3

NCO

MIXER

(OPTIONAL)

DDC 0

SYSREF±

REAL/I

REAL/Q

REAL/I

CONVERTER 0

Q CONVERTER 1

JESD204B

LANES

AT UP TO

15Gbps

ADC

SAMPLING

REAL/I

ADC

SAMPLING

REAL/Q

ADC

SAMPLING

REAL/I

ADC

SAMPLING

REAL/Q

SYNCHRONIZATION

CONTROL CIRCUITS

SYSREF

Figure 99. Two ADC + Four DDC Mode in Each Pair

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