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AD6684

Data Sheet

Rev. 0 | Page 56 of 107

FUNCTIONAL OVERVIEW

The block diagram in Figure 90 shows the flow of data through

each of the two JESD204B links from the sample input to the

physical output. The processing can be divided into layers that

are derived from the open source initiative (OSI) model widely

used to describe the abstraction layers of communications

systems. These layers are the transport layer, data link layer, and

physical layer (serializer and output driver).

Transport Layer

The transport layer handles packing the data (consisting of

samples and optional control bits) into JESD204B frames that

are mapped to 8-bit octets. These octets are sent to the data link

layer. The transport layer mapping is controlled by rules derived

from the link parameters. Tail bits are added to fill gaps where

required. The following equation can be used to determine the

number of tail bits within a sample (JESD204B word):

T = N΄ – N – CS

Data Link Layer

The data link layer is responsible for the low level functions of

passing data across the link. These functions include optionally

scrambling the data, inserting control characters for multichip

synchronization, lane alignment, or monitoring, and encoding

8-bit octets into 10-bit symbols. The data link layer is also

responsible for sending the initial lane alignment sequence

(ILAS), which contains the link configuration data used by the

receiver to verify the settings in the transport layer.

Physical Layer

The physical layer consists of the high speed circuitry clocked at

the serial clock rate. In this layer, parallel data is converted into

one, two, or four lanes of high speed differential serial data.

JESD204B LINK ESTABLISHMENT

The AD6684 JESD204B transmitter (Tx) interface operates in

Subclass 1 as defined in the JEDEC Standard 204B (July 2011

specification). The link establishment process is divided into the

following steps: code group synchronization and SYNCINB±AB/

SYNCINB±CD, initial lane alignment sequence, and user data

and error correction.

Code Group Synchronization (CGS) and SYNCINB±

The CGS is the process by which the JESD204B receiver finds

the boundaries between the 10-bit symbols in the stream of

data. During the CGS phase, the JESD204B transmit block

transmits /K28.5/ characters. The receiver must locate /K28.5/

characters in its input data stream using clock and data recovery

(CDR) techniques.

The receiver issues a synchronization request by asserting the

SYNCINB±AB and SYNCINB±CD pins of the AD6684 low.

The JESD204B Tx then begins sending /K/ characters. After the

receiver synchronizes, it waits for the correct reception of at

least four consecutive /K/ symbols. It then deasserts SYNCINB±AB

and SYNCINB±CD. The AD6684 then transmits an ILAS on

the following local multiframe clock (LMFC) boundary.

For more information on the code group synchronization

phase, refer to the JEDEC Standard JESD204B, July 2011,

Section 5.3.3.1.

The SYNCINB±AB and SYNCINB±CD pin operation can also

be controlled by the SPI. The SYNCINB±AB and SYNCINB±CD

signals are differential LVDS mode signals by default, but can

also be driven single-ended. For more information on configuring

the SYNCINB±AB and SYNCINB±CD pin operation, refer to

Initial Lane Alignment Sequence (ILAS)

The ILAS phase follows the CGS phase and begins on the next

LMFC boundary. The ILAS consists of four mulitframes, with

an /R/ character marking the beginning and an /A/ character

marking the end. The ILAS begins by sending an /R/ character

followed by 0 to 255 ramp data for one multiframe. On the

second multiframe, the link configuration data is sent, starting

with the third character. The second character is a /Q/ character

to confirm that the link configuration data follows. All

undefined data slots are filled with ramp data. The ILAS

sequence is never scrambled.

The ILAS sequence construction is shown in Figure 91. The

four multiframes include the following:



Multiframe 1. Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).



Multiframe 2. Begins with an /R/ character followed by a

/Q/ (/K28.4/) character, followed by link configuration

parameters over 14 configuration octets (see Table 32) and

ends with an /A/ character. Many of the parameter values

are of the value – 1 notation.



Multiframe 3. Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).



Multiframe 4. Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

K K R D

D A R Q C

C D

D A R D

D A D

START OF

ILAS

START OF LINK

CONFIGURATION DATA

END OF

MULTIFRAME

START OF

USER DATA

Figure 91. Initial Lane Alignment Sequence

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