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AD6684 Datasheet(PDF) 80 Page - Analog Devices

Part # AD6684
Description  135 MHz Quad IF Receiver
PDF  107 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6684 Datasheet(HTML) 80 Page - Analog Devices

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AD6684
Data Sheet
Rev. 0 | Page 80 of 107
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x0585
JESD204B
map JTX
LID 1
configuration
Reserved
Lane 1 LID value
0x02
R/W
0x058B JESD204B
map JTX
SCR L
configuration
JESD204B
scrambling
(SCR)
Reserved
JESD204B lanes (L)
0x81
R/W
0x058C JESD204B
map JTX F
configuration
Number of octets per frame (F)
0x01
R
0x058D JESD204B
map JTX K
configuration
Reserved
Number of frames per multiframe (K)
0x1F
R/W
0x058E
JESD204B
map JTX M
configuration
Number of converters per link
0x01
R
0x058F
JESD204B
map JTX
CS N
configuration
Number of control bits
(CS) per sample
Reserved
ADC converter resolution (N)
0x0F
R/W
0x0590
JESD204B
map JTX
Subclass
Version NP
configuration
Subclass support
ADC number of bits per sample (N')
0x2F
R/W
0x0591
JESD204B
map JTX JV S
configuration
Reserved
Samples per converter frame cycle (S)
0x20
R
0x0592
JESD204B
map JTX
HD CF
configuration
HD value
Reserved
Control words per frame clock cycle per link (CF)
0x00
R
0x05A0 JESD204B
map JTX
Checksum 0
configuration
Checksum 0 checksum value for SERDOUTAB0±/SERDOUTCD0±
0xC3
R
0x05A1 JESD204B
map JTX
Checksum 1
configuration
Checksum 1 checksum value for SERDOUTAB1±/SERDOUTCD1±
0xC4
R
0x05B0 JESD204B
map JTX lane
power-down
Reserved
JESD204B lane 1
power-down
Reserved
JESD-
204B
Lane 0
power-
down
0xFA
R/W
0x05B2 JESD204B
map JTX
Lane Assign-
ment 1
Reserved
SERDOUTAB0±/SERDOUTCD0± lane
assignment
0x00
R/W
0x05B3 JESD204B
map JTX
Lane Assign-
ment 2
Reserved
SERDOUTAB1±/SERDOUTCD1± lane
assignment
0x11
R/W
0x05C0 JESD204B
map
JESD204B
serializer
drive adjust
Reserved
Swing voltage for SERDOUTAB1±/
SERDOUTCD1±
Reserved
Swing voltage for SERDOUTAB0±/
SERDOUTCD0±
0x11
R/W
0x05C4 JESD204B
serializer
preemph-
asis
selection
register for
Logical
Lane 0
Post tab
polarity
Sets post tab level
Pretab
polarty
Sets pretab level
0x0
R/W



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